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3.6.1 Block Diagram
Figure 3.6.1 shows an overall block diagram for the DMAC.
SDRAM Controller
INTC (Interrupt Controller)
Interrupt REQ
7
DMAnV
→DMAC or micro DMA request
source setting
DMAR
→DMAC or micro DMA soft start
setting
DMAB
→Micro DMA burst setting
DMASEL
→DMAC or micro DMA select
setting
Note: "n" denotes a channel number. Micro DMA has eight channels (0 to 7) and DMA has six channels (0 to 5).
LCD Controller
Bus ACK
Bus REQ
CPU
0
DMASn
→Micro DMA source address setting
DMADn
→Micro DMA destination address setting
Micro DMA REQ,
DMACn
Micro DMA Channel
→Micro DMA transfer count setting
DMAMn
Micro DMA ACK,
INTTCn
→Micro DMA mode setting
DMAC
DMA REQ,
DMA Channel
HDMASn
DMA ACK,
INTDMAn
→DMA source address setting
HDMADn
→DMA destination address setting
HDMACAn
→DMA transfer count A setting
HDMACBn
→DMA transfer count B setting
HDMAMn
→DMA mode setting
HDMAE
→DMA operation enable/disable
HDMATR
→DMA maximum bus occupancy
time setting, mode setting
Figure 3.6.1 Overall Block Diagram
92CZ26A-89
Address Bus
State
Address Bus
Data Bus
State
31
0
Address Bus
Data Bus
State
15
0
7
0
31
0
Address Bus
State
Data Bus
15
0
7
0
TMP92CZ26A
Bus
Multiplexer
Source Memory, I/O
Address Bus
Data Bus
State
Destination Memory, I/O
Address Bus
Data Bus
State
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