Toshiba H1 Series Data Book page 446

(a) Single packet mode
This is data sequence of single packet mode when CPU bus interface is used.
Figure 3.16.15 is receiving sequence. Figure 3.16.16 is transmitting sequence.
Main of this chapter is access to FIFO. Data sequence with USB host refer to
chapter 5.
Endpoint 0 can't be changed mode for exclusive single packet mode. Single
packet and dual packet of endpoint 1 to 3 can change by setting Epx_SINGLE
register. When transferring, don't change packet.
Wait receiving data
DATASET = 0
DATASET register
• Check bit of EPx_DSET_A
DATASET = 1
SIZE register
RD receiving data of size in
appricable endpoint
Figure 3.16.15 Receiving Sequence in Single Packet Mode
IDLE
Receive valid data
DATASET register
• Set bit of EPx_D SET_A
• Assert EPx_DATASET signal
Interrupt by EPx_FULLA
Check DATASET register
• Size of SIZE_A_L confirmation
•
Size of SIZE_A_H confirmation
• Clear receiving data in FIFO
• Clear applicable bit of DATASET
register
92CZ26A-443
TMP92CZ26A