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LCDCTL0 <LCP0OC> is used to control the output timing of the LCP0 signal. When
<LCP0OC>=0, the LCP0 signal is always output. When <LCP0OC>=1, the LCP0
signal is output only when valid data is output.
LCP0 signal LCP0OC=1
LCP0 signal LCP0OC=0
bit Symbol
LCDCTL0
Read/Write
(0285H)
After reset
PIP function
0: Disable
1: Enable
Function
Note: When select STN mode, LCP0 is output at valid data only regardless of the setting of <LCP0OC> bit.
The phase of the LCP0 signal can be inverted by the setting of LCDCTL1<LCP0P>.
LVSYNC
LHSYNC
LLOAD
LGOEn
LFR
All signal changes
LCP0
LCP0P=0
LCP0
LCP0P=1
LD23-LD0
bit Symbol
LCDCTL1
Read/Write
(0286H)
After reset
LCP0
phase
Function
0: Rising
1: Falling
LCD Control 0 Register
7
6
5
PIPE
ALL0
FRMON
R/W
R/W
R/W
0
0
0
Segment
Frame divide
data
setting
0: Normal
0: Disable
1: Enable
1: Always
output "0"
LCD Control 1 Register
7
6
LCP0P
LHSP
LVSP
R/W
R/W
R/W
1
0
LHSYNC
LVSYNC
phase
phase
0: Rising
0: Rising
1: Falling
1: Falling
92CZ26A-522
4
3
–
R/W
0
Always
write "0"
5
4
3
LLDP
R/W
1
0
LLOAD
phase
0: Rising
1: Falling
TMP92CZ26A
2
1
DLS
LCP0OC
START
R/W
R/W
0
0
FR signal
LCP0 (Note)
LCDC
LCP0/Line
0: Always
operation
selection
output
1: At valid
0: Stop
1: Start
0: Line
data only
1: LCP0
LLOAD
width
0: At setting
in register
1: At valid
data only
2
1
LVSW1
LVSW0
R/W
0
LVSYNC
enable time control
00 : 1 clock of LHSYNC
01 : 2 clocks of LHSYNC
10 : 3 clocks of LHSYNC
11 : Reserved
0
R/W
0
0
R/W
0
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