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The following block diagram illustrates this mode.
Selector
TB0IN0
φT1
φT4
φT16
Selector
TB0RG0-WR
TB0RUN<TB0RDE>
The following example shows how to set 16-bit PPG output mode:
7
←
TB0RUN
0
←
TB0RG0
*
*
←
TB0RG1
*
*
←
TB0RUN
1
← X
TB0FFCR
←
TB0MOD
0
←
PPFC
–
←
TB0RUN
1
X: Don't care, −: No change
16-bit up counter
UC10
Match
16-bit comparator
TB0RG0H/L
Register buffer 0
Internal data bus
Figure 3.13.11 Block Diagram of 16-Bit Mode
6
5
4
3
2
1
0
0
X
X
–
–
X
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
0
X
X
–
0
X
0
X
0
0
1
1
1
0
0
1
0
0
1
*
*
(** = 01, 10, 11)
1
–
–
–
–
–
X
0
X
X
–
1
X
1
92CZ26A-310
TB0RUN<TB0RUN> TB0OUT0 (PPG output)
Clear
16-bit comparator
TB0RG1H/L
Disable the TB0RG0 double buffer and stop TMRB0.
Set the duty ratio
(16 bit)
Set the frequency
(16 bit)
Enable the TB0RG0H/L double buffer.
(The duty and frequency are changed on an INTTB01
interrupt.)
Set the mode to invert TB0FF0 at the match with
TB0RG0H/L/TB0RG1H/L. Set TB0FF0 to 0.
Select the internal clock as the input clock and disable
the capture function.
Set PP6 to function as TB0OUT0
Start TMRB0.
TMP92CZ26A
F/F
(TB0FF0)
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