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3.6.3
DMAC Operation Description
(1) Overall flowchart
Figure 3.6.9 shows a flowchart for DMAC operation when an interrupt (DMA) is
requested.
Interrupt (DMA) request
Interrupt specified by
DMA start vector?
Yes
Interrupt request F/F clear
& bus REQ assert
No
Bus ACK?
Yes
Internal timer start
HDMASn read
HDMADn write
Timer match?
No
No
HDMACAn -1=0?
Yes
Bus REQ deassert
HDMACBn -1=0?
No
END
Figure 3.6.9 Overall Flowchart
92CZ26A-96
To general-purpose interrupt or
micro DMA processing flow
No
Yes
Yes
INTDMAn assert
TMP92CZ26A
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