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When it writes data to FIFO in transmitting, confirm condition of two packets,
and consider the order of priority. When transfer data number is set, set to which
packet A and packet B, judge by PACKET_ACTIVE bit. Packet that bit is set to 0 is
bit that transfer now.
In transmitting and receiving, logic of PACKET_ACTIVE bit is reversed.
Therefore, please caution in transmitting.
Below is this sequence.
Wait transmitting event
Interrupt by EPx_EMPTY_A (B)
Check DATASET register
DATASET = 0
DATASET = 1
Wait
transmitting
rest data
If transmitting finish normally,
It clears applicable
bit of DATASET.
Figure 3.16.18 Transmitting Sequence in Dual Packet Mode
DATASETregister
• Check bit of EPx_DSET_A
• Check bit of EPx_DSET_B
Transmitting number > payload × 2
• Write number of payload × 2 in
applicable endpoint
• Total = Total − payload × 2
If transmitting number reach to
payload, DATASET set 1 to
applicable bit of register
Wait IN token
92CZ26A-446
IDLE
Transmitting event
Transmittind
data distinction
Transmitting number < payload × 2
• Write number of transmitting
number
• Total = 0
EOP register
Write 0 to only bit of applicable
endpoint
Wait transmitting
• Accessing to EOP register is needed in
• Control transfer type is only single mode
Finish
transmitting
TMP92CZ26A
transmitting short packet
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