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Bit symbol
SDCMM
Read/Write
(0253H)
After reset
Function
Note 1: <SCMM2:0> is automatically cleared to "000" after the specified command is issued. Before writing the next
command, make sure that <SCMM2:0> is "000". In the case of the Self Refresh Entry command, however,
<SCMM2:0> is not cleared to "000" by execution of this command. Thus, this register can be used as a flag for
checking whether or not Self Refresh is being performed.
Note 2: The Self Refresh Exit command can only be specified while Self Refresh is being performed.
Bit symbol
SDBLS
Read/Write
(0254H)
After reset
Function
SDRAM Command Register
7
6
5
SDRAM HDMA Burst Length Select Register
7
6
5
SDBL5
0
For HDMA5 For HDMA4 For HDMA3 For HDMA2 For HDMA1 For HDMA0
Figure 3.10.1 Control Registers
92CZ26A-222
4
3
2
SCMM2
0
Command issue
000: Don't care
001: Initialization sequence
a. Precharge All command
b. Eight Auto Refresh commands
c. Mode Register Set command
010: Precharge All command
100: Reserved
101: Self Refresh Entry command
110: Self Refresh Exit command
Others: Reserved
4
3
SDBL4
SDBLS
SDBL2
R/W
0
0
HDMA burst length
0: 1 Word read / Single write
1: Full page read / Burst write
TMP92CZ26A
1
0
SCMM1
SCMM0
R/W
0
0
(Note 1) (Note 2)
2
1
0
SDBL1
SDBL0
0
0
0
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