Toshiba H1 Series Data Book page 200

(e) External read/write cycle (4 waits +
SDCLK
(80 MHz)
CSn
A23 to 0
RD SRxxB
D15 to 0
SRWR , SRxxB
WRxx
D15 to 0
WAIT
(f) External read bus cycle (4 waits +
External write bus cycle (4 waits +
T1
SDCLK
(80 MHz)
CSn
A23 to 0
RD SRxxB
D15 to 0
SRWR , SRxxB
WRxx
D15 to 0
WAIT
T1 T2 T3
T2 T3
T4∼T7
TCWS
Output
TCWS
Sampling
92CZ26A-197
pin input mode)
WAIT
T4 T5
Output
Sampling
pin input mode +TAC: 1f
WAIT
pin input mode + TAC: 1f
WAIT
T8
TW
Input
Sampling
TMP92CZ26A
T6
TW
Input
Sampling
+ TCRS: 1.5f
SYS
+ TCRH: 1f
SYS
+ TCWS/H: 1.5f
SYS
T10
T9
Read
Write
SYS
)
SYS
)
Read
Write