Toshiba H1 Series Data Book page 227

(b) Address multiplex function
In access cycles, the A0 to A15 pins output low/column multiplexed addresses. The
multiplex width is set by SDACR<SMUXW1:0>. Table3.10.2 shows the relationship
between the multiplex width and low/column addresses.
92CZ26A Pin
Name
Type A
<SMUXW> = 00
A0 A9
A1 A10
A2 A11
A3 A12
A4 A13
A5 A14
A6 A15
A7 A16
A8 A17
A9 A18
A10 A19
A11 A20
A12 A21
A13 A22
A14 A23
A15 EA24
*AP: Auto Precharge
(c) Burst length
When the CPU accesses the SDRAM, the burst length is fixed to 1-word read/single write.
When the LCDC accesses the SDRAM, the burst length is fixed to full page.
The burst length can be selected for SDRAM read and write accesses by HDMA if the
following conditions are satisfied:
• The HDMA transfer mode is an increment mode.
• Transfers are made between the SDRAM and internal RAM or internal I/O.
In other cases, HDMA operation can only be performed in 1-word read/single write mode.
Use SDBLS<SDBL5:0> to set the burst length for each HDMA channel.
Table3.10.2 Address Multiplex
SDRAM Access Cycle Address
Row Address
Type B
<SMUXW> = 01 <SMUXW> = 10
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
EA24
EA25
92CZ26A-224
Column Address
Type C
A11 A1
A12 A2
A13 A3
A14 A4
A15 A5
A16 A6
A17 A7
A18 A8
A19 A9
A20 A10
A21 AP *
A22
A23
Row Address
EA24
EA25
EA26
TMP92CZ26A