Toshiba H1 Series Data Book page 593

32bit micro controller tlcs-900/h1 series
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3.22.1
Block Diagram
[Melody Generator]
MELFH
<MELON>
Low-speed
clock
MELALMC<FC1:0>
[Alarm Generator]
Internal data bus
MELFH, MELFL register
Comparator (CP0)
Stop and Clear
12bit counter (UC0)
15bit conter (UC1)
4096 Hz
8bit counter
(UC2)
Alarm wave form
generator
ALM register
Internal data bus
Figure 3.22.1MLD Block Diagram
92CZ26A-590
Reset
MELOUT
Invert
F/F
Clear
Edge
detectior
ALMINT
<IALM4E:0E>
MELOUT
Invert
ALMOUT
MELALMC
<ALMINV>
Reset
TMP92CZ26A
INTALM0 (8192Hz)
INTALM1 (512 Hz)
INTALM2 (64 Hz)
INTALM3 (2 Hz)
INTALM4 (1 Hz)
Selector
MELALMC
<MELALM>
INTALM
MLDALM pin

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