Toshiba H1 Series Data Book page 651

(2) Write cycle (0 waits)
X1
t
CL
SDCLK
WAIT
A0~A23
CSn
R/
W
t
AW
WRxx
D0~D15
t
RDO
RD
SRxxB
t
SAS
SRWR
Note1: The phase relation between X1 input signal and the other signals is undefined.
Note2: The above timing chart show an example of basic bus
pins timing can be adjusted by memory controller timing adjust function.
t
OSC
t
CYC
t
CH
t t
TK KT
t
WK
t
t
Data output
t
SBW
t
SDS
t
SWP
92CZ26A-648
t
WA
t
WW SWR
t
DW WD
t
SDH
timing. The , R/ W ,
CSn
TMP92CZ26A
, , ,
RD WRxx SRxxB SRWR