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(15) 16-bit timer (1/2)
Symbol
Name
Address
TMRB0
TB0RUN
RUN
1180H
register
TMRB0
1182H
TB0MOD
MODE
(Prohibit
register
RMW)
TMRB0
1183H
Flip-Flop
TB0FFCR
(Prohibit
control
RMW)
register
16 bit timer
1188H
TB0RG0L
register 0
(Prohibit
low
RMW)
16 bit timer
1189H
TB0RG0H
register 0
(Prohibit
high
RMW)
118AH
16 bit timer
TB0RG1L
(Prohibit
register low
RMW)
16 bit timer
118BH
TB0RG1H
register 1
(Prohibit
high
RMW)
Capture
TB0CP0L
register 0
118CH
low
Capture
TB0CP0H
register 0
118DH
high
Capture
TB0CP1L
register 1
118EH
low
Capture
TB0CP1H
register 1
118FH
high
7
6
5
−
TB0RDE
R/W
R/W
0
0
Always
Double
write "0".
buffer
0: disable
1: enable
−
−
TB0CP0I
R/W
W*
0
0
1
Always write "00".
Software
capture
control
0: Execute
1: Undefined
−
−
TB0CT1
W*
1
1
0
Always write "11".
TB1FF0 inversion trigger
0: Disable trigger
* Always read as "11".
1: Enable trigger
When
capture
UC10 to
TB0CP1H/L
92CZ26A-734
4
3
2
I2TB0
TB0PRUN
R/W
R/W
0
TMRB0
IDLE2
prescaler
0: Stop
1: Operate
0: Stop and clear
1: Run (Count up)
TB0CPM1 TB0CPM0
TB0CLE
R/W
0
0
Control
Capture timing
Up
00: Disable
counter
INT6 occurs at rising
0:Clear
edge
Disable
01: TB0IN0 ↑
1:Clear
INT6 occurs at rising
Enable
edge
10: TB0IN0 ↑ TB0IN0 ↓
INT6 occurs at falling
edge
11: TA1OUT ↑
TA1OUT ↓
INT6 occurs at rising
edge
TB0C0T1
TB0E1T1
TB0E0T1 TB0FF0C1 TB0FF0C0
R/W
0
0
When
When UC10
When UC10
capture
matches
matches
UC10 to
with
with
TB0CP0H/L
TB0RG1H/L
TB0RG0H/L
−
W
0
−
W
0
−
W
0
−
W
0
−
R
Undefined
−
R
Undefined
−
R
Undefined
−
R
Undefined
TMP92CZ26A
1
0
TB0RUN
R/W
0
0
Up
counter
(UC10)
TB0CLK1 TB0CLK0
0
0
0
TMRB1 source clock
00: TB0IN0 input
01: φT1
10: φT4
11: φT16
W*
0
1
1
Control TB1FF0
00: Invert
01: Set
10: Clear
11: Don't care
* Always read as "11".
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