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Toshiba TLCS-870/C Series Manual

Toshiba TLCS-870/C Series Manual

8 bit microcontroller
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8 Bit Microcontroller
TLCS-870/C Series
TMP86PM29BUG

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  • Page 1 8 Bit Microcontroller TLCS-870/C Series TMP86PM29BUG...
  • Page 2 It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
  • Page 3 TMP86PM29BUG The Functional Differences on Products basis: TMP86CM29L, TMP86Cx29B, TMP86CH21 and TMP86Cx20 TMP86C829B TMP86CH21 TMP86C420 Products name TMP86CM29L TMP86CH29B TMP86CH21A TMP86C820 TMP86CM29B C829: 8K bytes C420: 4K bytes 32 K bytes CH29: 16K bytes 16K bytes C820: 8K bytes CM29: 32K bytes C829: 512bytes 1.5K bytes CH29: 1.5K bytes...
  • Page 4 TMP86PM29BUG The Functional Differences on Products basis: TMP86C829B/CH29B/CM29B/PM29A/ PM29B/FM29/CM29L. TMP86PM29A Products name TMP86C829B TMP86CH29B TMP86CM29B TMP86FM29 TMP86CM29L TMP86PM29B 8K bytes 16K bytes 32K bytes 32K bytes 32K bytes 32K bytes (MASK) (MASK) (MASK) (OTP) (FLASH) (MASK) 512 bytes 1.5K bytes 128 bytes 128 bytes (Flash memory control/status registers...
  • Page 5 TMP86PM29BUG Halt/Operate Condition Wait Time‘ Peripherals Halt Halt After reset release /fc [s] Changing from STOP mode to NORMAL mode Halt Operate /fc [s] (at EEPCR<MNPWDW>="1" Changing from STOP mode to SLOW mode Halt Operate /fc [s] (at EEPCR<MNPWDW>="1") Changing from IDLE0/1/2 mode to NORMAL mode Halt Operate /fc [s]...
  • Page 6 TMP86PM29BUG...
  • Page 7 Revision History Date Revision 2007/10/11 First Release 2008/8/29 Contents Revised...
  • Page 8 Caution in Setting the UART Noise Rejection Time When UART is used, settings of RXDNC are limited depending on the transfer clock specified by BRG. The com- bination "O" is available but please do not select the combination "–". The transfer clock generated by timer/counter interrupt is calculated by the following equation : Transfer clock [Hz] = Timer/counter source clock [Hz] ÷...

  • Page 10: Table Of Contents

    Table of Contents TMP86PM29BUG Features ............1 Pin Assignment .
  • Page 11 3.4.2.2 Using data transfer instructions 3.4.3 Interrupt return ............................42 Software Interrupt (INTSW) ......... . 43 3.5.1 Address error detection ..........................
  • Page 12 Configuration ........... . . 71 Control .
  • Page 13 11.8.2 Data Receive Operation ........................126 11.9 Status Flag ........... . 127 11.9.1 Parity Error............................
  • Page 14 15.2.2 Frame frequency..........................156 15.2.3 Driving method for LCD driver ......................157 15.2.3.1 When using the booster circuit (LCDCR<BRES>="1") 15.2.3.2 When using an external resistor divider (LCDCR<BRES>="0") 15.3 LCD Display Operation ......... . . 159 15.3.1 Display data setting ..........................

  • Page 16: Tmp86Pm29Bug

    • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by impli- cation or otherwise under any patents or other rights of TOSHIBA or the third parties.
  • Page 17 1.1 Features TMP86PM29BUG 7. 8-bit timer counter : 4 ch - Timer, Event counter, Programmable divider output (PDO), Pulse width modulation (PWM) output, Programmable pulse generation (PPG) modes 8. 8-bit UART/SIO : 1 ch 9. 10-bit successive approximation type AD converter - Analog input: 8 ch 10.

  • Page 18: Pin Assignment

    TMP86PM29BUG 1.2 Pin Assignment SEG2 P54(SEG19) SEG1 P53(SEG20) SEG0 P52(SEG21) COM3 P51(SEG22) COM2 P50(SEG23) COM1 P17(SEG24/ COM0 P16(SEG25/TXD/SO) P15(SEG26/RXD/SI) P14(SEG27/INT3) P13(SEG28/INT2) P12(SEG29/INT1) P11(SEG30) ) P30 P10(SEG31) (TC3/ ) P31 PDO3/PWM3 AVDD (TC4/ ) P32 PDO4/PWM4/PPG4 VAREF (TC6/ ) P33 PDO6/PWM6/PPG6 P67(AIN7/STOP5) Figure 1-1 Pin Assignment Page 3...

  • Page 19: Block Diagram

    1.3 Block Diagram TMP86PM29BUG 1.3 Block Diagram Figure 1-2 Block Diagram Page 4...

  • Page 20: Pin Names And Functions

    TMP86PM29BUG 1.4 Pin Names and Functions The TMP86PM29BUG has MCU mode and PROM mode. Table 1-1 shows the pin functions in MCU mode. The PROM mode is explained later in a separate chapter. Table 1-1 Pin Names and Functions(1/3) Pin Name Pin Number Input/Output Functions...
  • Page 21 1.4 Pin Names and Functions TMP86PM29BUG Table 1-1 Pin Names and Functions(2/3) Pin Name Pin Number Input/Output Functions PORT56 SEG17 LCD segment output 17 PORT55 SEG18 LCD segment output 18 PORT54 SEG19 LCD segment output 19 PORT53 SEG20 LCD segment output 20 PORT52 SEG21 LCD segment output 21...
  • Page 22 TMP86PM29BUG Table 1-1 Pin Names and Functions(3/3) Pin Name Pin Number Input/Output Functions PORT71 SEG14 LCD segment output 14 PORT70 SEG15 LCD segment output 15 SEG7 LCD segment output 7 SEG6 LCD segment output 6 SEG5 LCD segment output 5 SEG4 LCD segment output 4 SEG3...
  • Page 23 1.4 Pin Names and Functions TMP86PM29BUG Page 8...

  • Page 24: Operational Description

    TMP86PM29BUG 2. Operational Description 2.1 CPU Core Functions The CPU core consists of a CPU, a system clock controller, and an interrupt controller. This section provides a description of the CPU core, the program memory, the data memory, and the reset circuit. 2.1.1 Memory Address Map The TMP86PM29BUG memory is composed OTP, RAM, DBR(Data buffer register) and SFR(Special func- TMP86PM29BUG...

  • Page 25: System Clock Controller

    2. Operational Description 2.2 System Clock Controller TMP86PM29BUG The data memory contents become unstable when the power supply is turned on; therefore, the data memory should be initialized by an initialization routine. Example :Clears RAM to “00H”. (TMP86PM29BUG) HL, 0040H ;...
  • Page 26 TMP86PM29BUG Low-frequency clock High-frequency clock XOUT XOUT XTIN XTIN XTOUT XTOUT (Open) (Open) (c) Crystal (d) External oscillator (a) Crystal/Ceramic (b) External oscillator resonator Figure 2-3 Examples of Resonator Connection Note:The function to monitor the basic clock directly at external is not provided for hardware, however, with dis- abling all interrupts and watchdog timers, the oscillation frequency can be adjusted by monitoring the pulse which the fixed frequency is outputted to the port by the program.

  • Page 27: Timing Generator

    2. Operational Description 2.2 System Clock Controller TMP86PM29BUG 2.2.2 Timing Generator The timing generator generates the various system clocks supplied to the CPU core and peripheral hardware from the basic clock (fc or fs). The timing generator provides the following functions. 1.

  • Page 28: Operation Mode Control Circuit

    The minimum instruction execution unit is called an “machine cycle”. There are a total of 10 different types of instructions for the TLCS-870/C Series: Ranging from 1-cycle instructions which require one machine cycle for execution to 10-cycle instructions which require 10 machine cycles for execution. A machine cycle consists of 4 states (S0 to S3), and each state consists of one main system clock.

  • Page 29: Dual-Clock Mode

    2. Operational Description 2.2 System Clock Controller TMP86PM29BUG IDLE1 mode In this mode, the internal oscillation circuit remains active. The CPU and the watchdog timer are halted; however on-chip peripherals remain active (Operate using the high-frequency clock). IDLE1 mode is started by SYSCR2<IDLE> = "1", and IDLE1 mode is released to NORMAL1 mode by an interrupt request from the on-chip peripherals or external interrupt inputs.
  • Page 30 TMP86PM29BUG Switching back and forth between SLOW1 and SLOW2 modes are performed by SYSCR2<XEN>. In SLOW1 and SLEEP modes, the input clock to the 1st stage of the divider is stopped; output from the 1st to 6th stages is also stopped. IDLE2 mode In this mode, the internal oscillation circuit remain active.
  • Page 31 2. Operational Description 2.2 System Clock Controller TMP86PM29BUG IDLE0 RESET Reset release mode Note 2 SYSCR2<TGHALT> = "1" SYSCR2<IDLE> = "1" SYSCR1<STOP> = "1" IDLE1 NORMAL1 mode mode Interrupt STOP pin input (a) Single-clock mode SYSCR2<XTEN> = "0" SYSCR2<XTEN> = "1" SYSCR2<IDLE>...
  • Page 32 TMP86PM29BUG System Control Register 1 SYSCR1 (0038H) STOP RELM RETM OUTEN (Initial value: 0000 00**) 0: CPU core and peripherals remain active STOP STOP mode start 1: CPU core and peripherals are halted (Start STOP mode) Release method for STOP 0: Edge-sensitive release RELM mode...

  • Page 33: Operating Mode Control

    2. Operational Description 2.2 System Clock Controller TMP86PM29BUG 2.2.4 Operating Mode Control 2.2.4.1 STOP mode STOP mode is controlled by the system control register 1, the pin input and key-on wakeup input STOP (STOP5 to STOP2) which is controlled by the STOP mode release control register (STOPCR). pin is also used both as a port P20 and an (external interrupt input 5) pin.
  • Page 34 TMP86PM29BUG Example 2 :Starting STOP mode from NORMAL mode with an INT5 interrupt. PINT5: TEST (P2PRD). 0 ; To reject noise, STOP mode does not start if F, SINT5 port P20 is at high (SYSCR1), 01010000B ; Sets up the level-sensitive release mode. ;...
  • Page 35 2. Operational Description 2.2 System Clock Controller TMP86PM29BUG STOP mode is released by the following sequence. 1. In the dual-clock mode, when returning to NORMAL2, both the high-frequency and low- frequency clock oscillators are turned on; when returning to SLOW1 mode, only the low- frequency clock oscillator is turned on.
  • Page 36 TMP86PM29BUG Figure 2-9 STOP Mode Start/Release Page 21...

  • Page 37: Idle1/2 Mode And Sleep1/2 Mode

    2. Operational Description 2.2 System Clock Controller TMP86PM29BUG 2.2.4.2 IDLE1/2 mode and SLEEP1/2 mode IDLE1/2 and SLEEP1/2 modes are controlled by the system control register 2 (SYSCR2) and maskable interrupts. The following status is maintained during these modes. 1. Operation of the CPU and watchdog timer (WDT) is halted. On-chip peripherals continue to operate.
  • Page 38 TMP86PM29BUG • Start the IDLE1/2 and SLEEP1/2 modes After IMF is set to "0", set the individual interrupt enable flag (EF) which releases IDLE1/2 and SLEEP1/2 modes. To start IDLE1/2 and SLEEP1/2 modes, set SYSCR2<IDLE> to “1”. • Release the IDLE1/2 and SLEEP1/2 modes IDLE1/2 and SLEEP1/2 modes include a normal release mode and an interrupt release mode.
  • Page 39 2. Operational Description 2.2 System Clock Controller TMP86PM29BUG Figure 2-11 IDLE1/2 and SLEEP1/2 Modes Start/Release Page 24...

  • Page 40: Idle0 And Sleep0 Modes (Idle0, Sleep0)

    TMP86PM29BUG 2.2.4.3 IDLE0 and SLEEP0 modes (IDLE0, SLEEP0) IDLE0 and SLEEP0 modes are controlled by the system control register 2 (SYSCR2) and the time base timer control register (TBTCR). The following status is maintained during IDLE0 and SLEEP0 modes. 1. Timing generator stops feeding clock to peripherals except TBT. 2.
  • Page 41 2. Operational Description 2.2 System Clock Controller TMP86PM29BUG • Start the IDLE0 and SLEEP0 modes Stop (Disable) peripherals such as a timer counter. To start IDLE0 and SLEEP0 modes, set SYSCR2<TGHALT> to “1”. • Release the IDLE0 and SLEEP0 modes IDLE0 and SLEEP0 modes include a normal release mode and an interrupt release mode.
  • Page 42 TMP86PM29BUG Figure 2-13 IDLE0 and SLEEP0 Modes Start/Release Page 27...
  • Page 43 2. Operational Description 2.2 System Clock Controller TMP86PM29BUG 2.2.4.4 SLOW mode SLOW mode is controlled by the system control register 2 (SYSCR2). The following is the methods to switch the mode with the warm-up counter. Switching from NORMAL2 mode to SLOW1 mode First, set SYSCR2<SYSCK>...
  • Page 44 TMP86PM29BUG Switching from SLOW1 mode to NORMAL2 mode First, set SYSCR2<XEN> to turn on the high-frequency oscillation. When time for stabilization (Warm up) has been taken by the timer/counter (TC4,TC3), clear SYSCR2<SYSCK> to switch the main system clock to the high-frequency clock. SLOW mode can also be released by inputting low level on the pin.
  • Page 45 2. Operational Description 2.2 System Clock Controller TMP86PM29BUG Figure 2-14 Switching between the NORMAL2 and SLOW Modes Page 30...

  • Page 46: Reset Circuit

    TMP86PM29BUG 2.3 Reset Circuit The TMP86PM29BUG has four types of reset generation procedures: An external reset input, an address trap reset, a watchdog timer reset and a system clock reset. Of these reset, the address trap reset, the watchdog timer and the system clock reset are a malfunction reset.

  • Page 47: Address Trap Reset

    2. Operational Description 2.3 Reset Circuit TMP86PM29BUG 2.3.2 Address trap reset If the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip RAM (when WDTCR1<ATAS> is set to “1”), DBR or the SFR area, address trap reset will be generated.
  • Page 48 TMP86PM29BUG Page 33...
  • Page 49 2. Operational Description 2.3 Reset Circuit TMP86PM29BUG Page 34...

  • Page 50: Interrupt Control Circuit

    TMP86PM29BUG 3. Interrupt Control Circuit The TMP86PM29BUG has a total of 19 interrupt sources excluding reset, of which 3 source levels are multi- plexed. Interrupts can be nested with priorities. Four of the internal interrupt sources are non-maskable while the rest are maskable.

  • Page 51: Interrupt Enable Register (Eir)

    3. Interrupt Control Circuit 3.2 Interrupt enable register (EIR) TMP86PM29BUG Interrupt latches are not set to “1” by an instruction. Since interrupt latches can be read, the status for interrupt requests can be monitored by software. Note: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0"...
  • Page 52 TMP86PM29BUG mally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulat- ing EF or IL should be executed before setting IMF="1". Example 1 :Enables interrupts individually and sets IMF ← ; IMF ← (EIRL), 1110100010100000B ;...
  • Page 53 3. Interrupt Control Circuit 3.2 Interrupt enable register (EIR) TMP86PM29BUG Interrupt Latches (Initial value: 00000000 000000**) ILH,ILL (003DH, 003CH) IL15 IL14 IL13 IL12 IL11 IL10 ILH (003DH) ILL (003CH) at RD at WR IL15 to IL2 Interrupt latches 0: No interrupt request 0: Clears the interrupt request 1: (Interrupt latch is not set.) 1: Interrupt request...

  • Page 54: Interrupt Source Selector (Intsel)

    TMP86PM29BUG 3.3 Interrupt Source Selector (INTSEL) Each interrupt source that shares the interrupt source level with another interrupt source is allowed to enable the interrupt latch only when it is selected in the INTSEL register. The interrupt controller does not hold interrupt requests corresponding to interrupt sources that are not selected in the INTSEL register.

  • Page 55: Saving/Restoring General-Purpose Registers

    3. Interrupt Control Circuit 3.4 Interrupt Sequence TMP86PM29BUG Interrupt service task 1-machine cycle Interrupt request Interrupt latch (IL) Execute Execute Execute Execute RETI instruction Interrupt acceptance instruction instruction instruction a − 1 a + 1 b + 1 b + 2 b + 3 c + 1 c + 2...

  • Page 56: Using Push And Pop Instructions

    TMP86PM29BUG 3.4.2.1 Using PUSH and POP instructions If only a specific register is saved or interrupts of the same source are nested, general-purpose registers can be saved/restored using the PUSH/POP instructions. Example :Save/store register using PUSH and POP instructions PINTxx: PUSH ;...

  • Page 57: Interrupt Return

    3. Interrupt Control Circuit 3.4 Interrupt Sequence TMP86PM29BUG Main task Interrupt Interrupt service task acceptance Saving registers Restoring registers Interrupt return Saving/Restoring general-purpose registers using PUSH/POP data transfer instruction Figure 3-4 Saving/Restoring General-purpose Registers under Interrupt Processing 3.4.3 Interrupt return Interrupt return instructions [RETI]/[RETN] perform as follows.

  • Page 58: Software Interrupt (Intsw)

    TMP86PM29BUG Note 1: It is recommended that stack pointer be return to rate before INTATRAP (Increment 3 times), if return inter- rupt instruction [RETN] is not utilized during interrupt service program under INTATRAP (such as Example Note 2: When the interrupt processing time is longer than the interrupt request generation time, the interrupt service task is performed but not the main task.
  • Page 59 3. Interrupt Control Circuit 3.8 External Interrupts TMP86PM29BUG Source Enable Conditions Release Edge Digital Noise Reject Pulses of less than 2/fc [s] are eliminated as noise. Pulses of 7/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, INT0 IMF EF4 INT0EN=1 Falling edge...
  • Page 60 TMP86PM29BUG External Interrupt Control Register EINTCR (0037H) INT1NC INT0EN INT3ES INT2ES INT1ES (Initial value: 00** 000*) 0: Pulses of less than 63/fc [s] are eliminated as noise INT1NC Noise reject time select 1: Pulses of less than 15/fc [s] are eliminated as noise 0: P63 input/output port INT0EN P63/...
  • Page 61 3. Interrupt Control Circuit 3.8 External Interrupts TMP86PM29BUG Page 46...

  • Page 62: Special Function Register (Sfr)

    TMP86PM29BUG 4. Special Function Register (SFR) The TMP86PM29BUG adopts the memory mapped I/O system, and all peripheral control and data transfers are performed through the special function register (SFR) or the data buffer register (DBR). The SFR is mapped on address 0000H to 003FH, DBR is mapped on address 0F80H to 0FFFH.
  • Page 63 4. Special Function Register (SFR) 4.1 SFR TMP86PM29BUG Address Read Write 0026H UARTCR2 0027H Reserved 0028H LCDCR 0029H P1LCR 002AH P5LCR 002BH P7LCR 002CH PWREG3 002DH PWREG4 002EH PWREG5 002FH PWREG6 0030H Reserved 0031H Reserved 0032H Reserved 0033H Reserved 0034H WDTCR1 0035H WDTCR2...

  • Page 64: Dbr

    TMP86PM29BUG 4.2 DBR Address Read Write 0F80H SEG1/0 0F81H SEG3/2 0F82H SEG5/4 0F83H SEG7/6 0F84H SEG9/8 0F85H SEG11/10 0F86H SEG13/12 0F87H SEG15/14 0F88H SEG17/16 0F89H SEG19/18 0F8AH SEG21/20 0F8BH SEG23/22 0F8CH SEG25/24 0F8DH SEG27/26 0F8EH SEG29/28 0F8FH SEG31/30 0F90H SIOBR0 0F91H SIOBR1 0F92H...
  • Page 65 4. Special Function Register (SFR) 4.2 DBR TMP86PM29BUG Note 2: − ; Cannot be accessed. Note 3: Write-only registers and interrupt latches cannot use the read-modify-write instructions (Bit manipulation instructions such as SET, CLR, etc. and logical operation instructions such as AND, OR, etc.). Page 50...
  • Page 66 TMP86PM29BUG 5. I/O Ports The TMP86PM29BUG has 6 parallel input/output ports (39 pins) as follows. Primary Function Secondary Functions External interrupt input, serial interface input/output, UART input/output and Port P1 8-bit I/O port segment output. Low-frequency resonator connections, external interrupt input, STOP mode Port P2 3-bit I/O port release signal input.

  • Page 67: Port P1 (P17 To P10)

    5. I/O Ports 5.1 Port P1 (P17 to P10) TMP86PM29BUG 5.1 Port P1 (P17 to P10) Port P1 is an 8-bit input/output port which is also used as an external interrupt input, serial interface input/output, UART input/output and segment output of LCD. When used as a segment pins of LCD, the respective bit of P1LCR should be set to “1”.

  • Page 68: Port P2 (P22 To P20)

    TMP86PM29BUG 5.2 Port P2 (P22 to P20) Port P2 is a 3-bit input/output port. It is also used as an external interrupt, a STOP mode release signal input, and low-frequency crystal oscillator con- nection pins. When used as an input port or a secondary function pins, respective output latch (P2DR) should be set to “1”.

  • Page 69: Port P3 (P33 To P30)

    5. I/O Ports 5.3 Port P3 (P33 to P30) TMP86PM29BUG 5.3 Port P3 (P33 to P30) Port P3 is a 4-bit input/output port. It is also used as a timer/counter input/output, divider output. When used as a timer/counter output or divider output, respective output latch (P3DR) should be set to “1”. It can be selected whether output circuit of P3 port is C-MOS output or a sink open drain individually, by setting P3OUTCR.

  • Page 70: Port P5 (P57 To P50)

    TMP86PM29BUG 5.4 Port P5 (P57 to P50) Port P5 is an 8-bit input/output port which is also used as a segment pins of LCD. When used as input port, the respective output latch (P5DR) should be set to “1”. During reset, the P5DR is initialized to “1”. When used as a segment pins of LCD, the respective bit of P5LCR should be set to “1”.

  • Page 71: Port P6 (P67 To P60)

    5. I/O Ports 5.5 Port P6 (P67 to P60) TMP86PM29BUG 5.5 Port P6 (P67 to P60) Port P6 is an 8-bit input/output port which can be configured as an input or an output in one-bit unit. Port P6 is also used as an analog input, Key on Wake up input, timer/counter input and external interrupt input.
  • Page 72 TMP86PM29BUG Port P6 control register P6DR (0006H) AIN7 AIN6 AIN5 AIN4 AIN3 AIN2 AIN1 AIN0 (Initial value: 0000 0000) STOP5 STOP4 STOP3 STOP2 ECNT ECIN INT0 P6CR (000CH) (Initial value: 0000 0000) AINDS = 1 (AD unused) AINDS = 0 (AD used) P6DR = “0”...

  • Page 73: Port P7 (P77 To P70)

    5. I/O Ports 5.6 Port P7 (P77 to P70) TMP86PM29BUG 5.6 Port P7 (P77 to P70) Port P7 is an 8-bit input/output port which is also used as a segment pins of LCD. When used as input port, the respective output latch (P7DR) should be set to “1”. During reset, the P7DR is initialized to “1”.

  • Page 74: Watchdog Timer (Wdt)

    TMP86PM29BUG 6. Watchdog Timer (WDT) The watchdog timer is a fail-safe system to detect rapidly the CPU malfunctions such as endless loops due to spu- rious noises or the deadlock conditions, and return the CPU to a system recovery routine. The watchdog timer signal for detecting malfunctions can be programmed only once as “reset request”...

  • Page 75: Watchdog Timer Control

    6. Watchdog Timer (WDT) 6.2 Watchdog Timer Control TMP86PM29BUG 6.2 Watchdog Timer Control The watchdog timer is controlled by the watchdog timer control registers (WDTCR1 and WDTCR2). The watch- dog timer is automatically enabled after the reset release. 6.2.1 Malfunction Detection Methods Using the Watchdog Timer The CPU malfunction is detected, as shown below.

  • Page 76: Watchdog Timer Enable

    TMP86PM29BUG Watchdog Timer Control Register 1 WDTCR1 (0034H) (ATAS) (ATOUT) WDTEN WDTT WDTOUT (Initial value: **11 1001) 0: Disable (Writing the disable code to WDTCR2 is required.) Write WDTEN Watchdog timer enable/disable 1: Enable only NORMAL1/2 mode SLOW1/2 mode DV7CK = 0 DV7CK = 1 Watchdog timer detection time Write...

  • Page 77: Watchdog Timer Disable

    6. Watchdog Timer (WDT) 6.2 Watchdog Timer Control TMP86PM29BUG 6.2.3 Watchdog Timer Disable To disable the watchdog timer, set the register in accordance with the following procedures. Setting the reg- ister in other procedures causes a malfunction of the microcontroller. 1.

  • Page 78: Watchdog Timer Reset

    TMP86PM29BUG 6.2.5 Watchdog Timer Reset When a binary-counter overflow occurs while WDTCR1<WDTOUT> is set to “1”, a watchdog timer reset request is generated. When a watchdog timer reset request is generated, the pin outputs a low-level sig- RESET nal and the internal hardware is reset. The reset time is maximum 24/fc [s] (1.5 µs @ fc = 16.0 MHz). Note:When a watchdog timer reset is generated in the SLOW1 mode, the reset time is maximum 24/fc (high-fre- quency clock) since the high-frequency clock oscillator is restarted.

  • Page 79: Address Trap

    6. Watchdog Timer (WDT) 6.3 Address Trap TMP86PM29BUG 6.3 Address Trap The Watchdog Timer Control Register 1 and 2 share the addresses with the control registers to generate address traps. Watchdog Timer Control Register 1 WDTCR1 (0034H) ATAS ATOUT (WDTEN) (WDTT) (WDTOUT) (Initial value: **11 1001)

  • Page 80: Address Trap Reset

    TMP86PM29BUG 6.3.4 Address Trap Reset While WDTCR1<ATOUT> is “1”, if the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip RAM (while WDTCR1<ATAS> is “1”), DBR or the SFR area, address trap reset will be generated.
  • Page 81 6. Watchdog Timer (WDT) 6.3 Address Trap TMP86PM29BUG Page 66...

  • Page 82: Time Base Timer (Tbt)

    TMP86PM29BUG 7. Time Base Timer (TBT) The time base timer generates time base for key scanning, dynamic displaying, etc. It also provides a time base timer interrupt (INTTBT). 7.1 Time Base Timer 7.1.1 Configuration fc/2 or fs/2 fc/2 or fs/2 fc/2 or fs/2 IDLE0, SLEEP0...

  • Page 83: Function

    7. Time Base Timer (TBT) 7.1 Time Base Timer TMP86PM29BUG Note 2: The interrupt frequency (TBTCK) must be selected with the time base timer disabled (TBTEN="0"). (The interrupt fre- quency must not be changed with the disable from the enable state.) Both frequency selection and enabling can be per- formed simultaneously.

  • Page 84: Divider Output (Dvo)

    TMP86PM29BUG 7.2 Divider Output ( Approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric buzzer drive. Divider output is from pin. 7.2.1 Configuration Output latch Data output DVO pin fc/2 or fs/2 fc/2 or fs/2 fc/2...
  • Page 85 7. Time Base Timer (TBT) 7.2 Divider Output (DVO) TMP86PM29BUG Example :1.95 kHz pulse output (fc = 16.0 MHz) ; DVOCK ← "00" (TBTCR) , 00000000B ; DVOEN ← "1" (TBTCR) , 10000000B Table 7-2 Divider Output Frequency ( Example : fc = 16.0 MHz, fs = 32.768 kHz ) Divider Output Frequency [Hz] DVOCK NORMAL1/2, IDLE1/2 Mode...

  • Page 86: Bit Timer/Counter (Tc1)

    TMP86PM29BUG 8. 18-Bit Timer/Counter (TC1) 8.1 Configuration Figure 8-1 Timer/Counter1 Page 71...

  • Page 87: Control

    8. 18-Bit Timer/Counter (TC1) 8.2 Control TMP86PM29BUG 8.2 Control The Timer/counter 1 is controlled by timer/counter 1 control registers (TC1CR1/TC1CR2), an 18-bit timer register (TREG1A), and an 8-bit internal window gate pulse setting register (TREG1B). Timer register TREG1AH − − −...
  • Page 88 TMP86PM29BUG Timer/counter 1 control register 1 TC1CR1 TC1C TC1S TC1CK TC1M (Initial value: 1000 1000) (0014H) Counter/overfow flag Clear Counter/overflow flag ( “1” is automatically set after clearing.) TC1C controll Not clear Counter/overflow flag Stop and counter clear and overflow flag clear TC1S TC1 start control Start...
  • Page 89 8. 18-Bit Timer/Counter (TC1) 8.2 Control TMP86PM29BUG Timer/Counter 1 control register 2 TC1CR2 SGEDG WGPSCK TC6OUT "0" (Initial value: 0000 000*) (0015H) External input clock (ECIN) edge Counts at the falling edge select Counts at the both (falling/rising) edges ECNT input Internal window gate pulse (TREG1B) Window gate pulse select (TC6)output...

  • Page 90: Function

    TMP86PM29BUG TC1 status register TC1SR HECF HEOVF "0" "0" "0" "0" "0" "0" (Initial value: 0000 0000) (0016H) Stop (during Tb) or disable HECF Operating Status monitor Under counting (during Ta) Read only No overflow HEOVF Counter overflow monitor Overflow status 8.3 Function TC1 has four operating modes.

  • Page 91: Event Counter Mode

    8. 18-Bit Timer/Counter (TC1) 8.3 Function TMP86PM29BUG Command Start Internal clock Up counter TREG1A Match detect Counter clear INTTC1 interrupt Figure 8-2 Timing chart for timer mode 8.3.2 Event Counter mode It is a mode to count up at the falling edge of the ECIN pin input. When using this mode, set TC1CR1<TC1CK>...

  • Page 92: Pulse Width Measurement Mode

    TMP86PM29BUG 8.3.3 Pulse Width Measurement mode In this mode, pulse widths are counted on the falling edge of logical AND-ed pulse between ECIN pin input (window pulse) and the internal clock. When using this mode, set TC1CR1<TC1CK> to suitable internal clock and then set TC1CR2<SEG>...

  • Page 93: Frequency Measurement Mode

    8. 18-Bit Timer/Counter (TC1) 8.3 Function TMP86PM29BUG 8.3.4 Frequency Measurement mode In this mode, the frequency of ECIN pin input pulse is measured. When using this mode, set TC1CR1<TC1CK> to the external clock. The edge of the ECIN input pulse is counted during “H” level of the window gate pulse selected by TC1CR2<SGP>.
  • Page 94 TMP86PM29BUG Table 8-3 Table Setting Ta and Tb (WGPSCK = 10, fc = 16 MHz) Setting Value Setting time Setting Value Setting time 16.38ms 8.19ms 15.36ms 7.17ms 14.34ms 6.14ms 13.31ms 5.12ms 12.29ms 4.10ms 11.26ms 3.07ms 10.24ms 2.05ms 9.22ms 1.02ms Table 8-4 Table Setting Ta and Tb (WGPSCK = 10, fs = 32.768 kHz) Setting Valuen Setting time Setting Value...
  • Page 95 8. 18-Bit Timer/Counter (TC1) 8.3 Function TMP86PM29BUG ECIN pin input Window gate pulse AND-ed pulse (Internal signal) Up counter Read Clear INTTC1 interrupt TC1CR1<TC1C> a) TC1CR2<SEG> = "0" TC1CR2<SEG> ECIN pin input Window gate pulse Up counter 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 Read Clear INTTC1 interrupt...

  • Page 96: Bit Timercounter (Tc3, Tc4)

    TMP86PM29BUG 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration PWM mode Overflow INTTC4 interrupt request fc/2 or fs/2 Clear 8-bit up-counter fc/2 TC4S fc/2 fc/2 PDO, PPG mode Toggle fc/2 16-bit mode TC4 pin PDO4/PWM4/ 16-bit PPG4 pin mode Clear TC4M TC4S Timer F/F4 TC4CK...

  • Page 97: Timercounter Control

    9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration TMP86PM29BUG 9.2 TimerCounter Control The TimerCounter 3 is controlled by the TimerCounter 3 control register (TC3CR) and two 8-bit timer registers (TTREG3, PWREG3). TimerCounter 3 Timer Register TTREG3 (001CH) (Initial value: 1111 1111) PWREG3 (002CH) (Initial value: 1111 1111)
  • Page 98 TMP86PM29BUG Note 7: The timer register settings are limited depending on the timer operating mode. For the detailed descriptions, see Table 9- Note 8: The operating clock fc in the SLOW or SLEEP mode can be used only as the high-frequency warm-up mode. Page 83...
  • Page 99 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration TMP86PM29BUG The TimerCounter 4 is controlled by the TimerCounter 4 control register (TC4CR) and two 8-bit timer registers (TTREG4 and PWREG4). TimerCounter 4 Timer Register TTREG4 (001DH) (Initial value: 1111 1111) PWREG4 (002DH) (Initial value: 1111 1111) Note 1: Do not change the timer register (TTREG4) setting while the timer is running.
  • Page 100 TMP86PM29BUG Note 6: To the TimerCounter in the 16-bit mode, select the source clock by programming TC3CR<TC3CK>. Set the timer start control and timer F/F control by programming TC4S and TFF4, respectively. Note 7: The operating clock settings are limited depending on the timer operating mode. For the detailed descriptions, see Table 9-1 and Table 9-2.
  • Page 101 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration TMP86PM29BUG Table 9-3 Constraints on Register Values Being Compared Operating mode Register Value 1≤ (TTREGn) ≤255 8-bit timer/event counter 1≤ (TTREGn) ≤255 8-bit PDO 2≤ (PWREGn) ≤254 8-bit PWM 1≤ (TTREG4, 3) ≤65535 16-bit timer/event counter 256≤...

  • Page 102: Function

    TMP86PM29BUG 9.3 Function The TimerCounter 3 and 4 have the 8-bit timer, 8-bit event counter, 8-bit programmable divider output (PDO), 8- bit pulse width modulation (PWM) output modes. The TimerCounter 3 and 4 (TC3, 4) are cascadable to form a 16- bit timer.

  • Page 103: 8-Bit Event Counter Mode (Tc3, 4)

    9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration TMP86PM29BUG TC4CR<TC4S> Internal Source Clock Counter TTREG4 Match detect Counter clear Counter clear Match detect INTTC4 interrupt request Figure 9-2 8-Bit Timer Mode Timing Chart (TC4) 9.3.2 8-Bit Event Counter Mode (TC3, 4) In the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the TCj pin.
  • Page 104 TMP86PM29BUG Example :Generating 1024 Hz pulse using TC4 (fc = 16.0 MHz) Setting port ÷ ÷ (TTREG4), 3DH : 1/1024 2 = 3DH (TC4CR), 00010001B : Sets the operating clock to fc/2 , and 8-bit PDO mode. (TC4CR), 00011001B : Starts TC4. Note 1: In the programmable divider output mode, do not change the TTREGj setting while the timer is running.
  • Page 105 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration TMP86PM29BUG Figure 9-4 8-Bit PDO Mode Timing Chart (TC4) Page 90...

  • Page 106: 8-Bit Pulse Width Modulation (Pwm) Output Mode (Tc3, 4)

    TMP86PM29BUG 9.3.4 8-Bit Pulse Width Modulation (PWM) Output Mode (TC3, 4) This mode is used to generate a pulse-width modulated (PWM) signals with up to 8 bits of resolution. The up-counter counts up using the internal clock. When a match between the up-counter and the PWREGj value is detected, the logic level output from the timer F/Fj is switched to the opposite state.
  • Page 107 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration TMP86PM29BUG Figure 9-5 8-Bit PWM Mode Timing Chart (TC4) Page 92...

  • Page 108: 16-Bit Timer Mode (Tc3 And 4)

    TMP86PM29BUG 9.3.5 16-Bit Timer Mode (TC3 and 4) In the timer mode, the up-counter counts up using the internal clock. The TimerCounter 3 and 4 are cascad- able to form a 16-bit timer. When a match between the up-counter and the timer register (TTREG3, TTREG4) value is detected after the timer is started by setting TC4CR<TC4S>...

  • Page 109: 16-Bit Event Counter Mode (Tc3 And 4)

    9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration TMP86PM29BUG 9.3.6 16-Bit Event Counter Mode (TC3 and 4) In the event counter mode, the up-counter counts up at the falling edge to the TC3 pin. The TimerCounter 3 and 4 are cascadable to form a 16-bit event counter. When a match between the up-counter and the timer register (TTREG3, TTREG4) value is detected after the timer is started by setting TC4CR<TC4S>...
  • Page 110 TMP86PM29BUG CLR (TC4CR).3: Stops the timer. CLR (TC4CR).7 : Sets the 4 pin to the high level. Note 3: To enter the STOP mode, stop the timer and then enter the STOP mode. If the STOP mode is entered with- out stopping of the timer when fc, fc/2 or fs is selected as the source clock, a pulse is output from the pin during the warm-up period time after exiting the STOP mode.
  • Page 111 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration TMP86PM29BUG Figure 9-7 16-Bit PWM Mode Timing Chart (TC3 and TC4) Page 96...

  • Page 112: 16-Bit Programmable Pulse Generate (Ppg) Output Mode (Tc3 And 4)

    TMP86PM29BUG 9.3.8 16-Bit Programmable Pulse Generate (PPG) Output Mode (TC3 and 4) This mode is used to generate pulses with up to 16-bits of resolution. The timer counter 3 and 4 are cascad- able to enter the 16-bit PPG mode. The counter counts up using the internal clock or external clock.
  • Page 113 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration TMP86PM29BUG Figure 9-8 16-Bit PPG Mode Timing Chart (TC3 and TC4) Page 98...

  • Page 114: Warm-Up Counter Mode

    TMP86PM29BUG 9.3.9 Warm-Up Counter Mode In this mode, the warm-up period time is obtained to assure oscillation stability when the system clocking is switched between the high-frequency and low-frequency. The timer counter 3 and 4 are cascadable to form a 16-bit TimerCounter.

  • Page 115: High-Frequency Warm-Up Counter Mode (Slow1 → Slow2 → Normal2 → Normal1)

    9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration TMP86PM29BUG 9.3.9.2 High-Frequency Warm-Up Counter Mode (SLOW1 → SLOW2 → NORMAL2 → NORMAL1) In this mode, the warm-up period time from a stop of the high-frequency clock fc to the oscillation sta- bility is obtained. Before starting the timer, set SYSCR2<XEN> to 1 to oscillate the high-frequency clock. When a match between the up-counter and the timer register (TTREG4, 3) value is detected after the timer is started by setting TC4CR<TC4S>...

  • Page 116: Bit Timercounter (Tc5, Tc6)

    TMP86PM29BUG 10. 8-Bit TimerCounter (TC5, TC6) 10.1 Configuration PWM mode Overflow INTTC6 interrupt request fc/2 or fs/2 Clear 8-bit up-counter fc/2 TC6S fc/2 fc/2 PDO, PPG mode Toggle fc/2 16-bit mode TC6 pin PDO6/PWM6/ 16-bit Timer, Event PPG6 pin mode Clear Counter mode TC6M...

  • Page 117: Timercounter Control

    10. 8-Bit TimerCounter (TC5, TC6) 10.1 Configuration TMP86PM29BUG 10.2 TimerCounter Control The TimerCounter 5 is controlled by the TimerCounter 5 control register (TC5CR) and two 8-bit timer registers (TTREG5, PWREG5). TimerCounter 5 Timer Register TTREG5 (001EH) (Initial value: 1111 1111) PWREG5 (002EH) (Initial value: 1111 1111)
  • Page 118 TMP86PM29BUG The TimerCounter 6 is controlled by the TimerCounter 6 control register (TC6CR) and two 8-bit timer registers (TTREG6 and PWREG6). TimerCounter 6 Timer Register TTREG6 (001FH) (Initial value: 1111 1111) PWREG6 (002FH) (Initial value: 1111 1111) Note 1: Do not change the timer register (TTREG6) setting while the timer is running. Note 2: Do not change the timer register (PWREG6) setting in the operating mode except the 8-bit and 16-bit PWM modes while the timer is running.
  • Page 119 10. 8-Bit TimerCounter (TC5, TC6) 10.1 Configuration TMP86PM29BUG Note 6: To the TimerCounter in the 16-bit mode, select the source clock by programming TC5CR<TC5CK>. Set the timer start control and timer F/F control by programming TC6S and TFF6, respectively. Note 7: The operating clock settings are limited depending on the timer operating mode. For the detailed descriptions, see Table 10-1 and Table 10-2.
  • Page 120 TMP86PM29BUG Table 10-3 Constraints on Register Values Being Compared Operating mode Register Value 1≤ (TTREGn) ≤255 8-bit timer/event counter 1≤ (TTREGn) ≤255 8-bit PDO 2≤ (PWREGn) ≤254 8-bit PWM 1≤ (TTREG6, 5) ≤65535 16-bit timer 256≤ (TTREG6, 5) ≤65535 Warm-up counter 2≤...

  • Page 121: Function

    10. 8-Bit TimerCounter (TC5, TC6) 10.1 Configuration TMP86PM29BUG 10.3 Function The TimerCounter 6 have the 8-bit timer, 8-bit event counter, 8-bit programmable divider output (PDO), 8-bit pulse width modulation (PWM) output modes. The TimerCounter 5 and 6 (TC5, 6) are cascadable to form a 16-bit timer.

  • Page 122: 8-Bit Event Counter Mode (Tc6)

    TMP86PM29BUG TC6CR<TC6S> Internal Source Clock Counter TTREG6 Match detect Counter clear Counter clear Match detect INTTC6 interrupt request Figure 10-2 8-Bit Timer Mode Timing Chart (TC6) 10.3.2 8-Bit Event Counter Mode (TC6) In the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the TCj pin. When a match between the up-counter and the TTREGj value is detected, an INTTCj interrupt is generated and the up-counter is cleared.
  • Page 123 10. 8-Bit TimerCounter (TC5, TC6) 10.1 Configuration TMP86PM29BUG Example :Generating 1024 Hz pulse using TC6 (fc = 16.0 MHz) Setting port ÷ ÷ (TTREG6), 3DH : 1/1024 2 = 3DH (TC6CR), 00010001B : Sets the operating clock to fc/2 , and 8-bit PDO mode. (TC6CR), 00011001B : Starts TC6.
  • Page 124 TMP86PM29BUG Figure 10-4 8-Bit PDO Mode Timing Chart (TC6) Page 109...

  • Page 125: 8-Bit Pulse Width Modulation (Pwm) Output Mode (Tc6)

    10. 8-Bit TimerCounter (TC5, TC6) 10.1 Configuration TMP86PM29BUG 10.3.4 8-Bit Pulse Width Modulation (PWM) Output Mode (TC6) This mode is used to generate a pulse-width modulated (PWM) signals with up to 8 bits of resolution. The up-counter counts up using the internal clock. When a match between the up-counter and the PWREGj value is detected, the logic level output from the timer F/Fj is switched to the opposite state.
  • Page 126 TMP86PM29BUG Figure 10-5 8-Bit PWM Mode Timing Chart (TC6) Page 111...

  • Page 127: 16-Bit Timer Mode (Tc5 And 6)

    10. 8-Bit TimerCounter (TC5, TC6) 10.1 Configuration TMP86PM29BUG 10.3.5 16-Bit Timer Mode (TC5 and 6) In the timer mode, the up-counter counts up using the internal clock. The TimerCounter 5 and 6 are cascad- able to form a 16-bit timer. When a match between the up-counter and the timer register (TTREG5, TTREG6) value is detected after the timer is started by setting TC6CR<TC6S>...

  • Page 128: 16-Bit Pulse Width Modulation (Pwm) Output Mode (Tc5 And 6)

    TMP86PM29BUG 10.3.6 16-Bit Pulse Width Modulation (PWM) Output Mode (TC5 and 6) This mode is used to generate a pulse-width modulated (PWM) signals with up to 16 bits of resolution. The TimerCounter 5 and 6 are cascadable to form the 16-bit PWM signal generator. The counter counts up using the internal clock.
  • Page 129 10. 8-Bit TimerCounter (TC5, TC6) 10.1 Configuration TMP86PM29BUG Example :Generating a pulse with 1-ms high-level width and a period of 32.768 ms (fc = 16.0 MHz) Setting ports (PWREG5), 07D0H : Sets the pulse width. (TC5CR), 33H : Sets the operating clock to fc/2 , and 16-bit PWM output mode (lower byte).
  • Page 130 TMP86PM29BUG Figure 10-7 16-Bit PWM Mode Timing Chart (TC5 and TC6) Page 115...

  • Page 131: 16-Bit Programmable Pulse Generate (Ppg) Output Mode (Tc5 And 6)

    10. 8-Bit TimerCounter (TC5, TC6) 10.1 Configuration TMP86PM29BUG 10.3.7 16-Bit Programmable Pulse Generate (PPG) Output Mode (TC5 and 6) This mode is used to generate pulses with up to 16-bits of resolution. The timer counter 5 and 6 are cascad- able to enter the 16-bit PPG mode.
  • Page 132 TMP86PM29BUG Figure 10-8 16-Bit PPG Mode Timing Chart (TC5 and TC6) Page 117...

  • Page 133: Warm-Up Counter Mode

    10. 8-Bit TimerCounter (TC5, TC6) 10.1 Configuration TMP86PM29BUG 10.3.8 Warm-Up Counter Mode In this mode, the warm-up period time is obtained to assure oscillation stability when the system clocking is switched between the high-frequency and low-frequency. The timer counter 5 and 6 are cascadable to form a 16-bit TimerCounter.

  • Page 134: High-Frequency Warm-Up Counter Mode (Slow1 → Slow2 → Normal2 → Normal1)

    TMP86PM29BUG 10.3.8.2 High-Frequency Warm-Up Counter Mode (SLOW1 → SLOW2 → NORMAL2 → NORMAL1) In this mode, the warm-up period time from a stop of the high-frequency clock fc to the oscillation sta- bility is obtained. Before starting the timer, set SYSCR2<XEN> to 1 to oscillate the high-frequency clock. When a match between the up-counter and the timer register (TTREG6, 5) value is detected after the timer is started by setting TC6CR<TC6S>...
  • Page 135 10. 8-Bit TimerCounter (TC5, TC6) 10.1 Configuration TMP86PM29BUG Page 120...

  • Page 136: Asynchronous Serial Interface (Uart )

    TMP86PM29BUG 11. Asynchronous Serial interface (UART ) 11.1 Configuration UART control register 1 Transmit data buffer Receive data buffer UARTCR1 TDBUF RDBUF Shift register Parity bit Shift register Stop bit INTTXD Noise rejection circuit INTRXD Transmit/receive clock fc/2 fc/2 fc/2 fc/13 fc/26 fc/52...

  • Page 137: Control

    11. Asynchronous Serial interface (UART ) 11.2 Control TMP86PM29BUG 11.2 Control UART is controlled by the UART Control Registers (UARTCR1, UARTCR2). The operating status can be moni- tored using the UART status register (UARTSR). UART Control Register1 UARTCR1 (0025H) STBT EVEN (Initial value: 0000 0000) Disable...
  • Page 138 TMP86PM29BUG UART Status Register UARTSR (0025H) PERR FERR OERR RBFL TEND TBEP (Initial value: 0000 11**) No parity error PERR Parity error flag Parity error No framing error FERR Framing error flag Framing error No overrun error OERR Overrun error flag Overrun error Read only...

  • Page 139: Transfer Data Format

    11. Asynchronous Serial interface (UART ) 11.3 Transfer Data Format TMP86PM29BUG 11.3 Transfer Data Format In UART, an one-bit start bit (Low level), stop bit (Bit length selectable at high level, by UARTCR1<STBT>), and parity (Select parity in UARTCR1<PE>; even- or odd-numbered parity by UARTCR1<EVEN>) are added to the transfer data.

  • Page 140: Transfer Rate

    TMP86PM29BUG 11.4 Transfer Rate The baud rate of UART is set of UARTCR1<BRG>. The example of the baud rate are shown as follows. Table 11-1 Transfer Rate (Example) Source Clock 16 MHz 8 MHz 4 MHz 76800 [baud] 38400 [baud] 19200 [baud] 38400 19200...

  • Page 141: Stop Bit Length

    11. Asynchronous Serial interface (UART ) 11.6 STOP Bit Length TMP86PM29BUG 11.6 STOP Bit Length Select a transmit stop bit length (1 bit or 2 bits) by UARTCR1<STBT>. 11.7 Parity Set parity / no parity by UARTCR1<PE> and set parity type (Odd- or Even-numbered) by UARTCR1<EVEN>. 11.8 Transmit/Receive Operation 11.8.1 Data Transmit Operation Set UARTCR1<TXE>...

  • Page 142: Status Flag

    TMP86PM29BUG 11.9 Status Flag 11.9.1 Parity Error When parity determined using the receive data bits differs from the received parity bit, the parity error flag UARTSR<PERR> is set to “1”. The UARTSR<PERR> is cleared to “0” when the RDBUF is read after read- ing the UARTSR.

  • Page 143: Receive Data Buffer Full

    11. Asynchronous Serial interface (UART ) 11.9 Status Flag TMP86PM29BUG UARTSR<RBFL> RXD pin Final bit Stop xxx0 ** xxxx0 1xxxx0 Shift register RDBUF yyyy UARTSR<OERR> After reading UARTSR then RDBUF clears OERR. INTRXD interrupt Figure 11-7 Generation of Overrun Error Note:Receive operations are disabled until the overrun error flag UARTSR<OERR>...

  • Page 144: Transmit End Flag

    TMP86PM29BUG Data write Data write xxxx yyyy zzzz TDBUF ***** 1 1xxxx0 * 1xxxx **** 1x ***** 1 1yyyy0 Shift register TXD pin Start Bit 0 Final bit Stop UARTSR<TBEP> After reading UARTSR writing TDBUF clears TBEP. INTTXD interrupt Figure 11-9 Generation of Transmit Data Buffer Empty 11.9.6 Transmit End Flag When data are transmitted and no data is in TDBUF (UARTSR<TBEP>...
  • Page 145 11. Asynchronous Serial interface (UART ) 11.9 Status Flag TMP86PM29BUG Page 130...

  • Page 146: Synchronous Serial Interface (Sio)

    TMP86PM29BUG 12. Synchronous Serial Interface (SIO) The TMP86PM29BUG has a clocked-synchronous 8-bit serial interface. Serial interface has an 8-byte transmit and receive data buffer that can automatically and continuously transfer up to 64 bits of data. Serial interface is connected to outside peripherl devices via SO, SI, SCK port. 12.1 Configuration SIO control / status register SIOSR...

  • Page 147: Control

    12. Synchronous Serial Interface (SIO) 12.2 Control TMP86PM29BUG 12.2 Control The serial interface is controlled by SIO control registers (SIOCR1/SIOCR2). The serial interface status can be determined by reading SIO status register (SIOSR). The transmit and receive data buffer is controlled by the SIOCR2<BUF>. The data buffer is assigned to address 0F90H to 0F97H for SIO in the DBR area, and can continuously transfer up to 8 words (bytes or nibbles) at one time.

  • Page 148: Serial Clock

    TMP86PM29BUG Always sets "00" except 8-bit transmit / receive mode. (Non wait) = 2T (Wait) WAIT Wait control = 4T (Wait) = 8T (Wait) 000: 1 word transfer 0F90H Write 001: 2 words transfer 0F90H ~ 0F91H only 010: 3 words transfer 0F90H ~ 0F92H 011: 4 words transfer...

  • Page 149: External Clock

    12. Synchronous Serial Interface (SIO) 12.3 Serial clock TMP86PM29BUG 12.3.1.1 Internal clock Any of six frequencies can be selected. The serial clock is output to the outside on the SCK pin. The SCK pin goes high when transfer starts. When data writing (in the transmit mode) or reading (in the receive mode or the transmit/receive mode) cannot keep up with the serial clock rate, there is a wait function that automatically stops the serial clock and holds the next shift operation until the read/write processing is completed.

  • Page 150: Shift Edge

    TMP86PM29BUG 12.3.2 Shift edge The leading edge is used to transmit, and the trailing edge is used to receive. 12.3.2.1 Leading edge Transmitted data are shifted on the leading edge of the serial clock (falling edge of the pin input/ output).

  • Page 151: Transfer Mode

    12. Synchronous Serial Interface (SIO) 12.6 Transfer Mode TMP86PM29BUG SCK pin SO pin INTSIO interrupt (a) 1 word transmit SCK pin SO pin INTSIO interrupt (b) 3 words transmit SCK pin SI pin INTSIO interrupt (c) 3 words receive Figure 12-6 Number of words to transfer (Example: 1word = 4bit) 12.6 Transfer Mode SIOCR1<SIOM>...
  • Page 152 TMP86PM29BUG SIOCR1<SIOS> is cleared, the operation will end after all bits of words are transmitted. That the transmission has ended can be determined from the status of SIOSR<SIOF> because SIOSR<SIOF> is cleared to “0” when a transfer is completed. When SIOCR1<SIOINH> is set, the transmission is immediately ended and SIOSR<SIOF> is cleared to “0”.

  • Page 153: 4-Bit And 8-Bit Receive Modes

    12. Synchronous Serial Interface (SIO) 12.6 Transfer Mode TMP86PM29BUG SCK pin SIOSR<SIOF> MSB of last word SO pin = min 3.5/fc [s] ( In the NORMAL1/2, IDLE1/2 modes) SODH = min 3.5/fs [s] (In the SLOW1/2, SLEEP1/2 modes) SODH Figure 12-9 Transmiiied Data Hold Time at End of Transfer 12.6.2 4-bit and 8-bit receive modes After setting the control registers to the receive mode, set SIOCR1<SIOS>...

  • Page 154: 8-Bit Transfer / Receive Mode

    TMP86PM29BUG Clear SIOS SIOCR1<SIOS> SIOSR<SIOF> SIOSR<SEF> SCK pin (Output) SI pin INTSIO Interrupt Read out Read out Figure 12-10 Receive Mode (Example: 8bit, 1word transfer, Internal clock) 12.6.3 8-bit transfer / receive mode After setting the SIO control register to the 8-bit transmit/receive mode, write the data to be transmitted first to the data buffer registers (DBR).
  • Page 155 12. Synchronous Serial Interface (SIO) 12.6 Transfer Mode TMP86PM29BUG Note:The buffer contents are lost when the transfer mode is switched. If it should become necessary to switch the transfer mode, end receiving by clearing SIOCR1<SIOS> to “0”, read the last data and then switch the trans- fer mode.

  • Page 156: Bit Ad Converter (Adc)

    TMP86PM29BUG 13. 10-bit AD Converter (ADC) The TMP86PM29BUG have a 10-bit successive approximation type AD converter. 13.1 Configuration The circuit configuration of the 10-bit AD converter is shown in Figure 13-1. It consists of control register ADCCR1 and ADCCR2, converted value register ADCDR1 and ADCDR2, a DA converter, a sample-hold circuit, a comparator, and a successive comparison circuit.

  • Page 157: Register Configuration

    13. 10-bit AD Converter (ADC) 13.2 Register configuration TMP86PM29BUG 13.2 Register configuration The AD converter consists of the following four registers: 1. AD converter control register 1 (ADCCR1) This register selects the analog channels and operation mode (Software start or repeat) in which to per- form AD conversion and controls the AD converter as it starts operating.
  • Page 158 TMP86PM29BUG AD Converter Control Register 2 ADCCR2 (000FH) IREFON "1" "0" (Initial value: **0* 000*) DA converter (Ladder resistor) connection Connected only during AD conversion IREFON control Always connected 000: 39/fc 001: Reserved 010: 78/fc AD conversion time select 011: 156/fc (Refer to the following table about the con- 100:...
  • Page 159 13. 10-bit AD Converter (ADC) 13.2 Register configuration TMP86PM29BUG Before or during conversion EOCF AD conversion end flag Conversion completed Read only During stop of AD conversion ADBF AD conversion BUSY flag During AD conversion Note 1: The ADCDR2<EOCF> is cleared to "0" when reading the ADCDR1. Therfore, the AD conversion result should be read to ADCDR2 more first than ADCDR1.

  • Page 160: Function

    TMP86PM29BUG 13.3 Function 13.3.1 Software Start Mode After setting ADCCR1<AMD> to “01” (software start mode), set ADCCR1<ADRS> to “1”. AD conver- sion of the voltage at the analog input pin specified by ADCCR1<SAIN> is thereby started. After completion of the AD conversion, the conversion result is stored in AD converted value registers (ADCDR1, ADCDR2) and at the same time ADCDR2<EOCF>...

  • Page 161: Register Setting

    13. 10-bit AD Converter (ADC) 13.3 Function TMP86PM29BUG ADCCR1<AMD> “11” “00” AD conversion start ADCCR1<ADRS> AD convert operation suspended. 1st conversion Conversion operation Conversion result is not stored. 2nd conversion result 3rd conversion result result Indeterminate ADCDR1,ADCDR2 1st conversion result 2nd conversion result 3rd conversion result ADCDR2<EOCF>...

  • Page 162: Stop/Slow Modes During Ad Conversion

    TMP86PM29BUG Example :After selecting the conversion time 19.5 µs at 16 MHz and the analog input channel AIN3 pin, perform AD con- version once. After checking EOCF, read the converted value, store the lower 2 bits in address 0009EH nd store the upper 8 bits in address 0009FH in RAM.

  • Page 163: Analog Input Voltage And Ad Conversion Result

    13. 10-bit AD Converter (ADC) 13.5 Analog Input Voltage and AD Conversion Result TMP86PM29BUG 13.5 Analog Input Voltage and AD Conversion Result The analog input voltage is corresponded to the 10-bit digital value converted by the AD as shown in Figure 13-4. conversion result VAREF...

  • Page 164: Precautions About Ad Converter

    Therefore, make sure the out- put impedance of the signal source in your design is 5 kΩ or less. Toshiba also recommends attaching a capac- itor external to the chip.
  • Page 165 13. 10-bit AD Converter (ADC) 13.6 Precautions about AD Converter TMP86PM29BUG Page 150...

  • Page 166: Key-On Wakeup (Kwu)

    TMP86PM29BUG 14. Key-on Wakeup (KWU) In the TMP86PM29BUG, the STOP mode is released by not only P20( ) pin but also four (STOP2 to INT5 STOP STOP5) pins. When the STOP mode is released by STOP2 to STOP5 pins, the pin needs to be used.
  • Page 167 14. Key-on Wakeup (KWU) 14.3 Function TMP86PM29BUG Also, each level of the STOP2 to STOP5 pins can be confirmed by reading corresponding I/O port data register, check all STOP2 to STOP5 pins "H" that is enabled by STOPCR before the STOP mode is started (Note2,3). Note 1: When the STOP mode released by the edge release mode (SYSCR1<RELM>...

  • Page 168: Lcd Driver

    TMP86PM29BUG 15. LCD Driver The TMP86PM29BUG has a driver and control circuit to directly drive the liquid crystal device (LCD). The pins to be connected to LCD are as follows: 1. Segment output port 32 pins (SEG31 to SEG0) 2. Common output port4 pins (COM3 to COM0) In addition, C0, C1, V1, V2, V3 pin are provided for the LCD driver’s booster circuit.

  • Page 169: Control

    15. LCD Driver 15.2 Control TMP86PM29BUG 15.2 Control The LCD driver is controlled using the LCD control register (LCDCR). The LCD driver’s display is enabled using the EDSP. LCD Driver Control Register LCDCR (0028H) EDSP BRES VFSEL DUTY (Initial value: 0000 0000) 0: Blanking EDSP LCD Display Control...

  • Page 170: Lcd Driving Methods

    TMP86PM29BUG 15.2.1 LCD driving methods As for LCD driving method, 4 types can be selected by LCDCR<DUTY>. The driving method is initialized in the initial program according to the LCD used. V LCD3 V LCD3 1/f F 1/f F −V LCD3 −V LCD3 Data "1"...

  • Page 171: Frame Frequency

    15. LCD Driver 15.2 Control TMP86PM29BUG 15.2.2 Frame frequency Frame frequency (f ) is set according to driving method and base frequency as shown in the following Table 15-1. The base frequency is selected by LCDCR<SLF> according to the frequency fc and fs of the basic clock to be used.

  • Page 172: Driving Method For Lcd Driver

    TMP86PM29BUG 15.2.3 Driving method for LCD driver In the TMP86PM29BUG, LCD driving voltages can be generated using either an internal booster circuit or an external resistor divider. This selection is made in LCDCR<BRES>. 15.2.3.1 When using the booster circuit (LCDCR<BRES>="1") When the reference voltage is connected to the V1 pin, the booster circuit boosts the reference voltage twofold (V2) or threefold (V3) to generate the output voltages for segment/common signals.
  • Page 173 15. LCD Driver 15.2 Control TMP86PM29BUG Keep the following condition. Reference voltage = 0.1 to 0.47 µF c) Reference pin = V3 Keep the following condition. V 3 = = 0.1 to 0.47 µF d) Reference pin = V3 Note 1: When the TMP86PM29BUG uses the booster circuit to drive the LCD, the power supply and capacitor for the booster cir- cuit should be connected as shown above.

  • Page 174: Lcd Display Operation

    TMP86PM29BUG The smaller the external resistor value, the higher the segment/common drive capability, but power con- sumption is increased. Conversely, the larger the external resistor value, the lower the segment/common drive capability, but power consumption is reduced. If the drive capability is insufficient, the LCD may not be displayed clearly.

  • Page 175: Blanking

    15. LCD Driver 15.3 LCD Display Operation TMP86PM29BUG Note: –: This bit is not used for display data Table 15-5 LCD Display Data Area (DBR) Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0F80H SEG1...

  • Page 176: Control Method Of Lcd Driver

    TMP86PM29BUG 15.4 Control Method of LCD Driver 15.4.1 Initial setting Figure 15-5 shows the flowchart of initialization. Example : To operate a 1/4 duty LCD of 32 segments × 4 com-mons at frame frequency fc/2 [Hz], and booster fre- quency fc/2 [Hz] (LCDCR), 01000001B ;...
  • Page 177 15. LCD Driver 15.4 Control Method of LCD Driver TMP86PM29BUG Example :To display using 1/4 duty LCD a numerical value which corresponds to the LCD data stored in data mem- ory at address 80H (when pins COM and SEG are connected to LCD as in Figure 15-6), display data become as shown in Table 15-6.
  • Page 178 TMP86PM29BUG Example 2: Table 15-6 shows an example of display data which are displayed using 1/2 duty LCD in the same way as Table 15-7. The connection between pins COM and SEG are the same as shown in Figure 15-7. COM0 SEG3 SEG0...

  • Page 179: Example Of Lcd Drive Output

    15. LCD Driver 15.4 Control Method of LCD Driver TMP86PM29BUG 15.4.3 Example of LCD drive output COM0 COM1 COM2 COM3 SEG0 SEG1 EDSP V LCD3 SEG0 V LCD3 SEG1 V LCD3 Display data area COM0 Address V LCD3 0F80H 1011 0101 COM1 V LCD3 COM2...
  • Page 180 TMP86PM29BUG SEG1 SEG0 SEG2 COM0 COM1 COM2 EDSP V LCD3 SEG0 V LCD3 SEG1 Display data area V LCD3 Address SEG2 0F80H *111 *010 V LCD3 0F81H **** *001 COM0 V LCD3 *: Don’t care COM1 V LCD3 COM2 V LCD3 COM0-SEG1 (Selected) −V LCD3...
  • Page 181 15. LCD Driver 15.4 Control Method of LCD Driver TMP86PM29BUG SEG3 COM0 COM2 COM1 EDSP V LCD3 SEG0 VLCD3 SEG1 Display data area VLCD3 Address SEG2 0F80H **01 **01 VLCD3 **11 **10 0F81H SEG3 VLCD3 *: Don’t care COM0 VLCD3 COM1 VLCD3 COM0-SEG1...
  • Page 182 TMP86PM29BUG SEG0 SEG1 SEG5 SEG6 SEG4 SEG2 COM0 SEG7 SEG3 Display data area EDSP Address V LCD3 0F80H ***0 ***1 SEG0 0F81H ***1 ***1 V LCD3 0F82H ***1 ***0 SEG4 0F83H ***0 ***1 V LCD3 SEG7 *: Don’t care V LCD3 COM0 V LCD3 COM0-SEG0...
  • Page 183 15. LCD Driver 15.4 Control Method of LCD Driver TMP86PM29BUG Page 168...

  • Page 184: Otp Operation

    TMP86PM29BUG 16. OTP operation This section describes the funstion and basic operationalblocks of TMP86PM29BUG. The TMP86PM29BUG has PROM in place of the mask ROM which is included in the TMP86Cx20,CH21,Cx29B. The configuration and func- tion are the same as the TMP86Cx20,CH21,Cx29B. In addition, TMP86PM29BUG operates as the single clock mode when releasing reset.

  • Page 185: Data Memory

    16. OTP operation 16.1 Operating mode TMP86PM29BUG 0000H 0000H 0000H Program 7FFFH 8000H 8000H Program Program Don’t use FFFFH FFFFH FFFFH Mask ROM MCU mode PROM mode (a) ROM size = 32 Kbytes 0000H 0000H 0000H Don’t use 4000H Program 7FFFH C000H C000H...

  • Page 186: Prom Mode

    TMP86PM29BUG does not support the electric signature mode, apply the ROM type of PROM programmer to TC571000D/AD. Note 2: No pin is applied to A16 pin of TC571000D/AD(Open) in PROM mode. Always set the adapter socket switch to the "N" side when using TOSHIBA’s adaptor socket. Page 171...
  • Page 187 16. OTP operation 16.1 Operating mode TMP86PM29BUG TMP86PM29BUG (12.5 V/5 V) setting pins TEST SEG0 SEG7 A15 ~ A0 D0 ~ D7 OPEN Refer to pin function 8 MHz GND setting pins for the other pin setting. XOUT Note 1: EPROM adaptor socket (TC571000 • 1M bit EPROM) Note 2: PROM programmer connection adaptor sockets BM11662 for TMP86PM29BUG Note 3: Inside pin name for TMP86PM29BUG...

  • Page 188: Programming Flowchart (High-Speed Program Writing)

    TMP86PM29BUG 16.1.2.1 Programming Flowchart (High-speed program writing) Start = 6.25 V = 12.75 V Address = Start address N = 0 Program 0.1 ms pulse N = N + 1 N = 25? Error Verify Address = Address + 1 Last address ? = 5 V = 5 V...

  • Page 189: Program Writing Using A General-Purpose Prom Programmer

    16. OTP operation 16.1 Operating mode TMP86PM29BUG 16.1.2.2 Program Writing using a General-purpose PROM Programmer 1. Recommended OTP adaptor BM11662 for TMP86PM29BUG 2. Setting of OTP adaptor Set the switch (SW1) to "N" side. 3. Setting of PROM programmer a. Set PROM type to TC571000D/AD. Vpp: 12.75 V (high-speed program writing mode) b.

  • Page 190: Input/Ouput Circuitry

    TMP86PM29BUG 17. Input/Ouput Circuitry 17.1 Control Pins The input/output circuitries of the TMP86PM29BUG control pins are shown below. Control Pin Input/Output Circuitry Remarks Osc. enable Resonator connecting pins (High-frequency) Input = 1.2 MΩ (typ.) XOUT Output = 1 kΩ (typ.) XOUT XTEN Osc.

  • Page 191: Input/Output Ports

    17. Input/Ouput Circuitry 17.2 Input/Output Ports TMP86PM29BUG 17.2 Input/Output Ports Port Input/Output Circuitry Remarks Initial "High-Z" P1LCR SEG output Sink open drain output Hysteresis input R = 100 Ω (typ.) Data output Input from output latch Pin input Initial "High-Z" P5LCR/P7LCR SEG output Sink open drain output...

  • Page 192: Electrical Characteristics

    TMP86PM29BUG 18. Electrical Characteristics 18.1 Absolute Maximum Ratings The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user.

  • Page 193: Recommended Operating Condition

    18. Electrical Characteristics 18.2 Recommended Operating Condition TMP86PM29BUG 18.2 Recommended Operating Condition The recommended operating conditions for a device are operating conditions under which it can be guaranteed that the device will operate as specified. If the device is used under operating conditions other than the recommended operating conditions (supply voltage, operating temperature range, specified AC/DC values etc.), malfunction may occur.

  • Page 194: Dc Characteristics

    TMP86PM29BUG 18.3 DC Characteristics = 0 V, Topr = −40 to 85°C) Parameter Symbol Pins Condition Typ. Unit Hysteresis voltage Hysteresis input – – TEST Sink open drain, Tri-state ± 2 µA = 5.5 V, V = 5.5 V/0 V Input current –...

  • Page 195: Ad Conversion Characteristics

    18. Electrical Characteristics 18.4 AD Conversion Characteristics TMP86PM29BUG 18.4 AD Conversion Characteristics = 0.0 V, 4.5 V ≤ V ≤ 5.5 V, Topr = −40 to 85°C) Parameter Symbol Condition Typ. Unit − 1.0 Analog reference voltage – AREF Power supply voltage of analog control circuit ∆V Analog reference voltage range (Note4)

  • Page 196: Ac Characteristics

    TMP86PM29BUG 18.5 AC Characteristics = 4.5 to 5.5 V, Topr = −40 to 85°C) = 0 V, V Parameter Symbol Condition Typ. Unit NORMAL1, 2 modes 0.25 – IDLE1, 2 modes µs Machine cycle time SLOW1, 2 modes 117.6 – 133.3 SLEEP1, 2 modes For external clock operation...

  • Page 197: Timer Counter 1 Input (Ecin) Characteristics

    18. Electrical Characteristics 18.6 Timer Counter 1 input (ECIN) Characteristics TMP86PM29BUG 18.6 Timer Counter 1 input (ECIN) Characteristics = 0 V, Topr = −40 to 85°C) Parameter Symbol Condition Typ. Unit Single edge count – – Frequency measurement mode = 4.5 to 5.5 V Both edge count –...

  • Page 198: Dc Characteristics, Ac Characteristics (Prom Mode)

    TMP86PM29BUG 18.7 DC Characteristics, AC Characteristics (PROM mode) 18.7.1 Read operation in PROM mode = 0 V, Topr = −40 to 85°C) Parameter Symbol Condition Typ. Unit High level input voltage – Low level input voltage – Power supply 4.75 5.25 Program supply of program 1.5tcyc +...

  • Page 199: Program Operation (High-Speed) (Topr = 25 ± 5°C)

    18. Electrical Characteristics 18.7 DC Characteristics, AC Characteristics (PROM mode) TMP86PM29BUG 18.7.2 Program operation (High-speed) (Topr = 25 ± 5°C) Parameter Symbol Condition Typ. Unit High level input voltage – Low level input voltage – Power supply 6.25 Program supply of program 12.5 12.75 13.0...

  • Page 200: Recommended Oscillating Conditions

    Note 3: For the resonators to be used with Toshiba microcontrollers, we recommend ceramic resonators manufactured by Murata Manufacturing Co., Ltd.
  • Page 201 18. Electrical Characteristics 18.9 Handling Precaution TMP86PM29BUG Page 186...

  • Page 202: Package Dimensions

    TMP86PM29BUG 19. Package Dimensions LQFP64-P-1010-0.50E Rev 02 Unit: mm 12.0 0.2 10.0 0.1 +0.07 1.25TYP -0.03 0.08 0.08 (0.5) 0.45~0.75 Page 187...
  • Page 203 19. Package Dimensions TMP86PM29BUG Page 188...
  • Page 204 This is a technical document that describes the operating functions and electrical specifications of the 8-bit microcontroller series TLCS-870/C (LSI). Toshiba provides a variety of development tools and basic software to enable efficient software development. These development tools have specifications that support advances in microcomputer hardware (LSI) and can be used extensively.

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