Toshiba H1 Series Data Book page 196

(6) Adjust Function for the timing of control signal
This function can change the timing of
signals and adjust the timing according to the set-up/hold time of the memories.
As for the
CSn
for only 1 CS area. While for
areas. As for CS area and EX area which is not set this function, it operates with base bus
timing (Refer to (7)).
This can not be used together with BnCSH<BnREC> function.
For control signal of SDRAM, it can be adjusted in SDRAM controller.
CSTMGCR<TxxSEL1:0>, WRTMGCR<TxxSEL1:0>
00
01
10
11
CSTMGCR<TAC1:0>
00
01
10
11
TAC:The delay from (A23-0) to (CSn, CSZx, CSXx, R/W).
WRTMGCR<TCWS/H1:0>
00
01
10
11
TCWS:The delay from (CSn) to (WRxx,SRWR,SRxxB).
TCWH:The delay from (WRxx,SRWR,SRxxB) to (CSn).
RDTMGCR0/1<BnTCRH1:0>
00
01
10
11
TCRH:The delay from (RD,SRxxB) to
, , , / and
R
CSZx CSXx W WRxx
and
RD
Change the timing of CS0 area
Change the timing of CS1 area
Change the timing of CS2 area
Change the timing of CS3 area
TAC = 0 × f
(Default)
SYS
TAC = 1 × f
SYS
TAC = 2 × f
SYS
(Reserved)
TCWS/H = 0.5 × f
(Default)
SYS
TCWS/H = 1.5 × f
SYS
TCWS/H = 2.5 × f
SYS
TCWS/H = 3.5 × f
SYS
TCRH = 0 × f
(Default)
SYS
TCRH = 1 × f
SYS
TCRH = 2 × f
SYS
TCRH = 3 × f
SYS
(CSn).
92CZ26A-193
, , , /
R
CSn CSZx CSXx W
, , (at write cycle), it can be changed
SRWR SRxxB
(at read cycle), it can be changed for all CS
SRxxB
TMP92CZ26A
, , , and
RD WRxx SRWR SRxxB