Toshiba H1 Series Data Book page 372

3.16.2 900/H1 CPU I/F
The 900/H1 CPU I/F is a bridge between 900/H1 CPU and UDC and it mainly works
following operations.
• INTUSB (interrupt from UDC) generation
• A bridge for SFR
• USB clock control (48 MHz)
3.16.2.1 SFRs
The 900/H1 CPU I/F have following SFRs to control UDC and USB transceiver.
• USB control
USBCR1
• USB interrupt control
USBINTFR1
USBINTFR2
USBINTFR3
USBINTFR4
USBINTMR1
USBINTMR2
USBINTMR3
USBINTMR4
(USB control register 1)
(USB interrupt flag register 1)
(USB interrupt flag register 2)
(USB interrupt flag register 3)
(USB interrupt flag register 4)
(USB interrupt mask register 1)
(USB interrupt mask register 2)
(USB interrupt mask register 3)
(USB interrupt mask register 4)
Figure 3.16.2 900/H1 CPU I/F SFR
Read/Write
Address
07F0H R/W
07F1H R/W
07F2H R/W
07F3H R/W
07F4H R/W
07F5H R/W
07F6H R/W
07F7H R/W
07F8H R/W
92CZ26A-369
SFR Symbol
USBINTFR1
USBINTFR2
USBINTFR3
USBINTFR4
USBINTMR1
USBINTMR2
USBINTMR3
USBINTMR4
USBCR1
TMP92CZ26A