Toshiba H1 Series Data Book page 91

3.6 DMAC (DMA Controller)
The TMP92CZ26A incorporates a DMA controller (DMAC) having six channels. This DMAC can
realize data transfer faster than the micro DMA function by the 900/H1 CPU.
The DMAC has the following features:
1) Six independent channels of DMA
2) Two types of transfer start requests
Hardware request (using an interrupt source connected with the INTC) or software
request can be selected for each channel.
3) Various source/destination combinations
The combination of transfer source and destination can be selected for each channel
from the following four types: memory to memory, memory to I/O, I/O to memory, I/O
to I/O.
4) Transfer address mode
Only the dual address mode is supported.
5) Dual-count mechanism and DMA end interrupt
Two count registers are provided to execute multiple DMA transfers by one DMA
request and to generate multiple DMA requests at a time. The DMA end interrupt
(INTDMA0 to INTDMA5) is also provided so that a general-purpose interrupt routine
can be used to prepare for the next processing.
6) Priorities among DMA channels (the same as the micro DMA acceptance specifications
of the INTC)
DMA requests are basically accepted in the order in which they are asserted. If more
than one request is asserted simultaneously or it looks as if two requests were
asserted simultaneously because one of the requests has been put on hold while other
processing was being performed, the smaller-numbered channel is given a higher
priority.
7) DMAC bus occupancy limiting function
The DMAC incorporates a special timer for limiting its bus occupancy time to avoid
excessive interference with the CPU or LCDC operation.
8) The DMAC can be used in HALT (IDLE2) mode.
92CZ26A-88
TMP92CZ26A