Toshiba H1 Series Data Book page 441

IDLE
Receive IN token
Confirm Token packet
• PID
• Address
• Endpoint
• Transfer mode
• Error
OK
Confirm Status
• Confirm STATUS register (status)
OK
Generate DATA PID
• Attach DATA0
• Confirm DATASIZE register
OK
Transmit data
Error transaction
Attach CRC
IDLE
ReceiveSOF
• FRAME noread
• BANK shift
Not receive SOF
Not renewal frame number
loss data
Figure 3.16.13 Control Flow in UDC (Isochronous transfer type (Transmission))
Error
Receive SOF
without transmitting data
Set LOST to FRAME register
Not renew FRAME number
Assert SOF
BANK B transaction
Shift FIFO BANKs
every receive SOF
BANK A transaction
92CZ26A-438
Invalid
Clear X condition (A)
Set FULL to STATUS
• Assert SOF
• Clear transmitting FIFO BANK A in preceding frame
• Clear DATASET register's BANK A bit
• Set DATASET register's BANK B bit
(Finish a write in previous frame)
• Set STATUS to READY
• Wait data for transmitting next frame (BANK A)
• Assert SOF
• Clear transmitting FIFO BANK B in preceding
frame
• Clear DATASET register's BANK B bit
• Set DATASET register's BANK A bit
(Finish a write in previous frame)
• Set STATUS to READY
TMP92CZ26A