Toshiba H1 Series Data Book page 648

4.3 AC Characteristics
The Following all AC regulation is the measurement result in following condition, if unless otherwise noted.
AC measuring condition
Clock of top column in above table shows system clock frequency, and "T" shows system
•
clock period [ns].
Output level: High = 0.7×3AV
•
Input level: High = 0.9×3AV
•
Note: In table, "Variable" shows the regulation at DVCC3A=3.0V~3.6V, DVCC1A=DVCC1B=DVCC1C=1.4~1.6V.
4.3.1 Basic Bus Cycle
Read cycle
No. Parameter
1 OSC period (X1/X2)
2 System clock period ( = T)
3 SDCLK low width
4 SDCLK high width
A0 ~ A23 valid → D0 ~ D15 input at 0
5-1
waits
A0 ~ A23 valid
5-2
→ D0 ~ D15 input at
falling →
6-1 D0 ~ D15 input at 0 waits
RD
falling
RD
6-2
→ D0 ~ D15 input at
7-1 low width at 0 waits
RD
7-2 low width at 4 waits
RD
8 A0 ~ A23 valid →
falling → SDCLK rising
9
RD
10 A0 ~ A23 valid → D0 ~ D15 hold
rising → D0 ~ D15 hold
11
RD
12 setup time
WAIT
hold time
13
WAIT
14 Data byte control access time
high width
15
RD
AC measuring condition
• Data_bus, Address_bus, various function control signal capacitance C
Note: The operation guarantee temprature: 80MHz:
CC
Symbol
t
OSC
t
CYC
t
CL
t
CH
t
AD
t
AD6
4 waits/6 waits
t
AD7
t
RD
t
RD
t
RD6
4 waits/6waits
t
RD7
t
RR
t
RR6
falling t
RD
AR
t
RK
t
HA
t
HR
t
TK
t
KT
t
SBA
t
RRH
92CZ26A-645
, Low = 0.3×3AV
CC CC
, Low = 0.1×3AV
CC
Variable
Min Max
100 166.6
12.5 266.6
0.5T − 3
0.5T − 3
2.0T − 18.0
6.0T − 18.0
8.0T - 18.0
1.5T − 18.0
1.5T − 18.0
5.5T − 18.0
5.5T − 18.0
1.5T − 10
5.5T − 10
0.5T − 5
0.5T − 5
0
0
3
2
1.5T − 18.0
0.5T − 5
Ta=0∼50°C, less than 60MHz: Ta=0∼70°C
TMP92CZ26A
80 MHz 60 MHz Unit
− −
12.5 16.6
3.25 5.3
3.25 5.3
7 15.3
−
82
−
82
−
7
−
0.75
−
73.6
ns
−
50.75
8.75 14.9
58.75 81.3
1.25 3.3
1.25 3.3
0 0
0 0
3 5
2 3
0.75 7
1.25 3.3
= 50 pF
L