Toshiba H1 Series Data Book page 105

(2) CPU + LDMA
The LCD controller performs DMA transfer (LDMA) after issuing a bus request to the
CPU and getting a bus acknowledgement.
If LDMA is not performed properly, the LCD display function cannot work properly.
Therefore, LDMA must have higher priority than the CPU. While LDMA is being
performed, the CPU cannot execute instructions.
To display data on the LCD using the LCD controller, it is necessary to estimate to what
degree LDMA would interfere with the CPU operation based on the display RAM type,
display RAM bus width, LCDD type, display pixel count, and display quality.
The time the CPU stops operation while the LCD controller transfers data for one line is
defined as "t (LDMA)", which is calculated as shown below for each display mode.
STOP
t (LDMA) = (SegNum × K / 8) × t
STOP
16-bit external SRAM
Internal RAM
16-bit external SDRAM
SegNum
K
Note 1: When SDRAM is used, the overhead time is added as shown below.
[s] = (SegNum × K/8) × t
t
STOP
Note 2: When internal RAM is used, the overhead time is added as shown below.
[s] = ( SegNum × K/8 ) × t
t
STOP
The CPU bus stop rate indicates what proportion of the 1-line data update time
t is taken up by t
LP STOP
CPU bus stop rate = t
LRD
: t = (2 + wait count) / f
LRD
: t = 1 / f
LRD
:t = 1 / f
LRD SYS
: Number of segments to be displayed
: Number of bits needed for displaying 1 pixel
Monochrome
4 gray scales
16 gray scales
256 colors
4096 colors
65536 colors
262144/16777216 colors
+ ((1/f
LRD SYS
+ (1/f
LRD
(LDMA) and is calculated as follows:
(LDMA) [s] / LHSYNC [period: s]
STOP
92CZ26A-102
[Hz] / 2
SYS
[Hz] / 4
SYS
[Hz] / 2
K = 1
K = 2
K = 4
K = 8
K = 12
K = 16
K = 24
) × 8)
)
SYS
TMP92CZ26A