Hitachi H8/3060 Manuals

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Hitachi H8/3060 Hardware Manual

Hitachi H8/3060 Hardware Manual (995 pages)

Single-Chip Microcomputer H8/3062 Series; H8/3062B Series; H8/3062F-ZTAT series; H8/3064F-ZTAT series  
Brand: Hitachi | Category: Computer Hardware | Size: 4.08 MB
Table of contents
Table Of Contents17................................................................................................................................................................
Section 1 Overview49................................................................................................................................................................
Table 1.1 Features50................................................................................................................................................................
Block Diagram55................................................................................................................................................................
Pin Description56................................................................................................................................................................
H8/3062f-ztat B-mask Version, H8/3064 Mask Rom B-mask Version59................................................................................................................................................................
Pin Functions61................................................................................................................................................................
Pin Assignments In Each Mode66................................................................................................................................................................
Notes On H8/3062f-ztat R-mask Version70................................................................................................................................................................
Product Type Names And Markings71................................................................................................................................................................
H8/3064 Mask Rom B-mask Version, H8/3062 Mask Rom B-mask Version H8/3061 Mask Rom B-mask Version, And H8/3060 Mask Rom B-mask Version72................................................................................................................................................................
Pin Arrangement73................................................................................................................................................................
Notes On Changeover To On-chip Mask Rom Versions And On-chip Mask Rom B-mask Versions75................................................................................................................................................................
Setting Oscillation Settling Wait Time76................................................................................................................................................................
Section 2 Cpu77................................................................................................................................................................
Differences From H8/300 Cpu78................................................................................................................................................................
Cpu Operating Modes79................................................................................................................................................................
Register Configuration80................................................................................................................................................................
General Registers81................................................................................................................................................................
Control Registers82................................................................................................................................................................
Initial Cpu Register Values83................................................................................................................................................................
Data Formats84................................................................................................................................................................
Memory Data Formats85................................................................................................................................................................
Figure 2.8 Memory Data Formats86................................................................................................................................................................
Instruction Set87................................................................................................................................................................
Instructions And Addressing Modes88................................................................................................................................................................
Tables Of Instructions Classified By Function89................................................................................................................................................................
Table 2.3 Data Transfer Instructions90................................................................................................................................................................
Table 2.4 Arithmetic Operation Instructions91................................................................................................................................................................
Table 2.5 Logic Operation Instructions93................................................................................................................................................................
Table 2.7 Bit Manipulation Instructions94................................................................................................................................................................
Table 2.8 Branching Instructions96................................................................................................................................................................
Table 2.9 System Control Instructions97................................................................................................................................................................
Basic Instruction Formats98................................................................................................................................................................
Notes On Use Of Bit Manipulation Instructions99................................................................................................................................................................
Addressing Modes And Effective Address Calculation101................................................................................................................................................................
Table 2.12 Absolute Address Access Ranges102................................................................................................................................................................
Effective Address Calculation103................................................................................................................................................................
Table 2.13 Effective Address Calculation104................................................................................................................................................................
Processing States107................................................................................................................................................................
Exception-handling State108................................................................................................................................................................
Exception Handling Operation109................................................................................................................................................................
Bus-released State110................................................................................................................................................................
Power-down State111................................................................................................................................................................
On-chip Supporting Module Access Timing112................................................................................................................................................................
Access To External Address Space113................................................................................................................................................................
Section 3 Mcu Operating Modes115................................................................................................................................................................
System Control Register (syscr)117................................................................................................................................................................
Operating Mode Descriptions120................................................................................................................................................................
Mode 6121................................................................................................................................................................
Memory Map In Each Operating Mode122................................................................................................................................................................
Reserved Areas123................................................................................................................................................................
H8/3062f-ztat B-mask Version, H8/3062 Mask Rom Version, And H8/3062 Mask Rom B-mask Version In Each Operating Mode124................................................................................................................................................................
B-mask Version In Each Operating Mode126................................................................................................................................................................
Figure 3.3 Memory Map Of H8/3060 Mask Rom Version And H8/3060 Mask Rom B-mask Version In Each Operating Mode128................................................................................................................................................................
Section 4 Exception Handling133................................................................................................................................................................
Exception Vector Table134................................................................................................................................................................
Table 4.2 Exception Vector Table135................................................................................................................................................................
Reset136................................................................................................................................................................
Figure 4.2 Reset Sequence (modes 1 And 3)137................................................................................................................................................................
Figure 4.3 Reset Sequence (modes 2 And 4)138................................................................................................................................................................
Interrupts After Reset139................................................................................................................................................................
Interrupts140................................................................................................................................................................
Stack Status After Exception Handling141................................................................................................................................................................
Notes On Stack Usage142................................................................................................................................................................
Figure 4.7 Operation When Sp Value Is Odd143................................................................................................................................................................
Section 5 Interrupt Controller145................................................................................................................................................................
Pin Configuration147................................................................................................................................................................
Interrupt Priority Registers A And B (ipra, Iprb)148................................................................................................................................................................
Irq Status Register (isr)153................................................................................................................................................................
Irq Enable Register (ier)154................................................................................................................................................................
Irq Sense Control Register (iscr)155................................................................................................................................................................
Interrupt Sources156................................................................................................................................................................
Internal Interrupts157................................................................................................................................................................
Table 5.3 Interrupt Sources, Vector Addresses, And Priority158................................................................................................................................................................
Interrupt Operation161................................................................................................................................................................
Figure 5.4 Process Up To Interrupt Acceptance When Ue = 1162................................................................................................................................................................
Figure 5.5 Interrupt Masking State Transitions (example)164................................................................................................................................................................
Figure 5.6 Process Up To Interrupt Acceptance When Ue = 0165................................................................................................................................................................
Interrupt Exception Handling Sequence166................................................................................................................................................................
Interrupt Response Time167................................................................................................................................................................
Usage Notes168................................................................................................................................................................
Instructions That Inhibit Interrupts169................................................................................................................................................................
Section 6 Bus Controller171................................................................................................................................................................
Access State Control Register (astcr)175................................................................................................................................................................
Wait Control Registers H And L (wcrh, Wcrl)176................................................................................................................................................................
Bus Release Control Register (brcr)180................................................................................................................................................................
Bus Control Register (bcr)181................................................................................................................................................................
Chip Select Control Register (cscr)183................................................................................................................................................................
Address Control Register (adrcr)184................................................................................................................................................................
Operation185................................................................................................................................................................
Version, H8/3062 Mask Rom Version, H8/3061 Mask Rom Version, H8/3062 Mask Rom B-mask Version, H8/3061 Mask Rom B-mask Version) (1)186................................................................................................................................................................
Figure 6.3 Memory Map In 16-mbyte Mode (h8/3060 Mask Rom Version H8/3060 Mask Rom B-mask Version) (2)187................................................................................................................................................................
Bus Specifications189................................................................................................................................................................
Memory Interfaces190................................................................................................................................................................
Address Output Method191................................................................................................................................................................
Figure 6.6 Example Of Consecutive External Space Accesses In Address Update Mode 2192................................................................................................................................................................
Basic Bus Interface193................................................................................................................................................................
Valid Strobes194................................................................................................................................................................
Memory Areas195................................................................................................................................................................
Basic Bus Control Signal Timing196................................................................................................................................................................
Figure 6.10 Bus Control Signal Timing For 8-bit, Two-state-access Area197................................................................................................................................................................
Wait Control203................................................................................................................................................................
Figure 6.17 Example Of Wait State Insertion Timing204................................................................................................................................................................
Idle Cycle205................................................................................................................................................................
Figure 6.19 Example Of Idle Cycle Operation (icis0 = 1)206................................................................................................................................................................
Pin States In Idle Cycle207................................................................................................................................................................
Figure 6.21 Example Of External Bus Master Operation209................................................................................................................................................................
Register And Pin Input Timing210................................................................................................................................................................
Breq Pin Input Timing211................................................................................................................................................................
Section 7 I/o Ports213................................................................................................................................................................
Port217................................................................................................................................................................
Register Descriptions221................................................................................................................................................................
Table 7.4 Input Pull-up Transistor States (port 2)223................................................................................................................................................................
Table 7.11 Port 6 Pin Functions In Modes 1 To 5235................................................................................................................................................................
Register Description237................................................................................................................................................................
Table 7.14 Port 8 Pin Functions In Modes 1 To 5241................................................................................................................................................................
Table 7.15 Port 8 Pin Functions In Modes 6 And 7242................................................................................................................................................................
Table 7.17 Port 9 Pin Functions246................................................................................................................................................................
Overview248................................................................................................................................................................
Figure 7.10 Port A Pin Configuration249................................................................................................................................................................
Table 7.19 Port A Pin Functions (modes 1, 2, 6, And 7)252................................................................................................................................................................
Table 7.20 Port A Pin Functions (modes 3 To 5)254................................................................................................................................................................
Table 7.21 Port A Pin Functions (modes 1 To 7)257................................................................................................................................................................
Figure 7.11 Port B Pin Configuration261................................................................................................................................................................
Table 7.23 Port B Pin Functions (modes 1 To 5)264................................................................................................................................................................
Table 7.24 Port B Pin Functions (modes 6 And 7)266................................................................................................................................................................
Section 8 16-bit Timer269................................................................................................................................................................
Table 8.1 16-bit Timer Functions270................................................................................................................................................................
Block Diagrams271................................................................................................................................................................
Figure 8.2 Block Diagram Of Channels 0 And 1272................................................................................................................................................................
Figure 8.3 Block Diagram Of Channel 2273................................................................................................................................................................
Timer Synchro Register (tsnc)277................................................................................................................................................................
Timer Mode Register (tmdr)278................................................................................................................................................................
Timer Interrupt Status Register A (tisra)281................................................................................................................................................................
Timer Interrupt Status Register B (tisrb)283................................................................................................................................................................
Timer Interrupt Status Register C (tisrc)286................................................................................................................................................................
Timer Counters (16tcnt)288................................................................................................................................................................
General Registers (gra, Grb)289................................................................................................................................................................
Timer Control Registers (16tcr)290................................................................................................................................................................
Timer I/o Control Register (tior)292................................................................................................................................................................
Timer Output Level Setting Register C (tolr)294................................................................................................................................................................
Cpu Interface296................................................................................................................................................................
Figure 8.6 Access To Timer Counter H (cpu Writes To 16tcnth, Upper Byte)297................................................................................................................................................................
Bit Accessible Registers298................................................................................................................................................................
Figure 8.12 Counter Setup Procedure (example)300................................................................................................................................................................
Figure 8.13 Free-running Counter Operation301................................................................................................................................................................
Figure 8.15 Count Timing For Internal Clock Sources302................................................................................................................................................................
Figure 8.17 Setup Procedure For Waveform Output By Compare Match (example)303................................................................................................................................................................
Figure 8.18 0 And 1 Output (toa = 1, Tob = 0)304................................................................................................................................................................
Figure 8.20 Output Compare Output Timing305................................................................................................................................................................
Figure 8.21 Setup Procedure For Input Capture (example)306................................................................................................................................................................
Synchronization307................................................................................................................................................................
Figure 8.24 Setup Procedure For Synchronization (example)308................................................................................................................................................................
Pwm Mode309................................................................................................................................................................
Figure 8.26 Setup Procedure For Pwm Mode (example)310................................................................................................................................................................
Figure 8.27 Pwm Mode (example 1)311................................................................................................................................................................
Figure 8.28 Pwm Mode (example 2)312................................................................................................................................................................
Phase Counting Mode313................................................................................................................................................................
Figure 8.30 Operation In Phase Counting Mode (example)314................................................................................................................................................................
Bit Timer Output Timing315................................................................................................................................................................
Figure 8.34 Timing Of Setting Of Imfa And Imfb By Input Capture317................................................................................................................................................................
Timing Of Clearing Of Status Flags318................................................................................................................................................................
Figure 8.38 Contention Between 16tcnt Word Write And Increment321................................................................................................................................................................
Figure 8.39 Contention Between 16tcnt Byte Write And Increment322................................................................................................................................................................
Figure 8.40 Contention Between General Register Write And Compare Match323................................................................................................................................................................
Figure 8.41 Contention Between 16tcnt Write And Overflow324................................................................................................................................................................
Figure 8.42 Contention Between General Register Read And Input Capture325................................................................................................................................................................
Figure 8.44 Contention Between General Register Write And Input Capture327................................................................................................................................................................
Table 8.7 (a) 16-bit Timer Operating Modes (channel 0)329................................................................................................................................................................
Table 8.7 (b) 16-bit Timer Operating Modes (channel 1)330................................................................................................................................................................
Table 8.7 (c) 16-bit Timer Operating Modes (channel 2)331................................................................................................................................................................
Section 9 8-bit Timers333................................................................................................................................................................
Time Constant Registers A (tcora)339................................................................................................................................................................
Time Constant Registers B (tcorb)340................................................................................................................................................................
Timer Control Register (8tcr)341................................................................................................................................................................
Timer Control/status Registers (8tcsr)344................................................................................................................................................................
Table 9.3 Operation Of Channels 0 And 1 When Bit Ice Is Set To 1 In 8tcsr1 Register347................................................................................................................................................................
Figure 9.5 8tcnt1 Access Operation (cpu Writes To 8tcnt1, Lower Byte)350................................................................................................................................................................
Compare Match Timing352................................................................................................................................................................
Input Capture Signal Timing353................................................................................................................................................................
Timing Of Status Flag Setting354................................................................................................................................................................
Operation With Cascaded Connection355................................................................................................................................................................
Input Capture Setting358................................................................................................................................................................
Interrupt359................................................................................................................................................................
A/d Converter Activation360................................................................................................................................................................
Contention Between 8tcnt Write And Increment362................................................................................................................................................................
Contention Between Tcor Write And Compare Match363................................................................................................................................................................
Contention Between Tcor Read And Input Capture364................................................................................................................................................................
Contention Between Counter Clearing By Input Capture And Counter Increment365................................................................................................................................................................
Contention Between Tcor Write And Input Capture366................................................................................................................................................................
Figure 9.24 Contention Between 8tcnt Byte Write And Increment In 16-bit Count Mode367................................................................................................................................................................
Contention Between Compare Matches A And B368................................................................................................................................................................
Table 9.8 Internal Clock Switchover And 8tcnt Operation369................................................................................................................................................................
Section 10 Programmable Timing Pattern Controller (tpc)371................................................................................................................................................................
Port B Data Direction Register (pbddr)376................................................................................................................................................................
Next Data Register A (ndra)377................................................................................................................................................................
Next Data Register B (ndrb)379................................................................................................................................................................
Next Data Enable Register A (ndera)381................................................................................................................................................................
Next Data Enable Register B (nderb)382................................................................................................................................................................
Tpc Output Control Register (tpcr)383................................................................................................................................................................
Tpc Output Mode Register (tpmr)385................................................................................................................................................................
Output Timing388................................................................................................................................................................
Normal Tpc Output389................................................................................................................................................................
Figure 10.5 Normal Tpc Output Example (five-phase Pulse Output)390................................................................................................................................................................
Non-overlapping Tpc Output391................................................................................................................................................................
Tpc Output Triggering By Input Capture393................................................................................................................................................................
Figure 10.10 Non-overlapping Operation And Ndr Write Timing395................................................................................................................................................................
Section 11 Watchdog Timer397................................................................................................................................................................
Timer Control/status Register (tcsr)400................................................................................................................................................................
Reset Control/status Register (rstcsr)402................................................................................................................................................................
Notes On Register Rewriting403................................................................................................................................................................
Figure 11.3 Format Of Data Written To Rstcsr404................................................................................................................................................................
Interval Timer Operation406................................................................................................................................................................
Timing Of Setting Of Watchdog Timer Reset Bit (wrst)407................................................................................................................................................................
Section 12 Serial Communication Interface409................................................................................................................................................................
Transmit Shift Register (tsr)415................................................................................................................................................................
Serial Mode Register (smr)416................................................................................................................................................................
Serial Control Register (scr)419................................................................................................................................................................
Serial Status Register (ssr)423................................................................................................................................................................
Bit Rate Register (brr)428................................................................................................................................................................
Table 12.3 Examples Of Bit Rates And Brr Settings In Asynchronous Mode429................................................................................................................................................................
Table 12.4 Examples Of Bit Rates And Brr Settings In Synchronous Mode432................................................................................................................................................................
Table 12.5 Maximum Bit Rates For Various Frequencies (asynchronous Mode)434................................................................................................................................................................
Table 12.6 Maximum Bit Rates With External Clock Input (asynchronous Mode)435................................................................................................................................................................
Table 12.8 Smr Settings And Serial Communication Formats438................................................................................................................................................................
Operation In Asynchronous Mode439................................................................................................................................................................
Table 12.10 Serial Communication Formats (asynchronous Mode)440................................................................................................................................................................
Figure 12.4 Sample Flowchart For Sci Initialization442................................................................................................................................................................
Figure 12.5 Sample Flowchart For Transmitting Serial Data443................................................................................................................................................................
Figure 12.7 Sample Flowchart For Receiving Serial Data445................................................................................................................................................................
Table 12.11 Receive Error Conditions447................................................................................................................................................................
Multiprocessor Communication448................................................................................................................................................................
Figure 12.10 Sample Flowchart For Transmitting Multiprocessor Serial Data450................................................................................................................................................................
Figure 12.12 Sample Flowchart For Receiving Multiprocessor Serial Data452................................................................................................................................................................
Synchronous Operation455................................................................................................................................................................
Figure 12.15 Sample Flowchart For Sci Initialization456................................................................................................................................................................
Figure 12.16 Sample Flowchart For Serial Transmitting457................................................................................................................................................................
Figure 12.17 Example Of Sci Transmit Operation458................................................................................................................................................................
Figure 12.18 Sample Flowchart For Serial Receiving459................................................................................................................................................................
Figure 12.19 Example Of Sci Receive Operation461................................................................................................................................................................
Figure 12.20 Sample Flowchart For Simultaneous Serial Transmitting And Receiving462................................................................................................................................................................
Sci Interrupts463................................................................................................................................................................
Figure 12.21 Receive Data Sampling Timing In Asynchronous Mode465................................................................................................................................................................
Figure 12.22 Example Of Synchronous Transmission466................................................................................................................................................................
Figure 12.23 Operation When Switching From Sck Pin Function To Port Pin Function467................................................................................................................................................................
Section 13 Smart Card Interface469................................................................................................................................................................
Data Format478................................................................................................................................................................
Figure 13.3 Smart Card Interface Data Format479................................................................................................................................................................
Register Settings480................................................................................................................................................................
Clock482................................................................................................................................................................
Table 13.6 Brr Settings For Typical Bit Rates (bits/s) (when N = 0)483................................................................................................................................................................
Transmitting And Receiving Data484................................................................................................................................................................
Figure 13.4 Timing Of Tend Flag Setting485................................................................................................................................................................
Figure 13.5 Sample Transmission Processing Flowchart486................................................................................................................................................................
Figure 13.6 Relation Between Transmit Operation And Internal Registers487................................................................................................................................................................
Figure 13.8 Sample Reception Processing Flowchart488................................................................................................................................................................
Figure 13.9 Timing For Fixing Cock Output489................................................................................................................................................................
Figure 13.10 Procedure For Stopping And Restarting The Clock490................................................................................................................................................................
Figure 13.12 Retransmission In Sci Receive Mode493................................................................................................................................................................
Section 14 A/d Converter495................................................................................................................................................................
A/d Control/status Register (adcsr)499................................................................................................................................................................
A/d Control Register (adcr)501................................................................................................................................................................
Figure 14.2 A/d Data Register Access Operation (reading H'aa40)503................................................................................................................................................................
Figure 14.3 Example Of A/d Converter Operation (single Mode, Channel 1 Selected)505................................................................................................................................................................
Scan Mode (scan = 1)506................................................................................................................................................................
Input Sampling And A/d Conversion Time508................................................................................................................................................................
External Trigger Input Timing509................................................................................................................................................................
Figure 14.7 Example Of Analog Input Protection Circuit511................................................................................................................................................................
Figure 14.9 A/d Converter Accuracy Definitions (1)512................................................................................................................................................................
Figure 14.10 A/d Converter Accuracy Definitions (2)513................................................................................................................................................................
Figure 14.11 Analog Input Circuit (example)514................................................................................................................................................................
Section 15 D/a Converter515................................................................................................................................................................
D/a Standby Control Register (dastcr)520................................................................................................................................................................
Figure 15.2 Example Of D/a Converter Operation521................................................................................................................................................................
D/a Output Control522................................................................................................................................................................
Section 16 Ram523................................................................................................................................................................
Overview Of Flash Memory (h8/3062f-ztat, H8/3062f-ztat R-mask Version)528................................................................................................................................................................
Flash Memory Register Descriptions531................................................................................................................................................................
Erase Block Register (ebr)534................................................................................................................................................................
Ram Control Register (ramcr)535................................................................................................................................................................
Figure 17.2 Example Of Rom Area/ram Area Overlap536................................................................................................................................................................
Flash Memory Status Register (flmsr)537................................................................................................................................................................
On-board Programming Mode538................................................................................................................................................................
Figure 17.3 Boot Mode539................................................................................................................................................................
Figure 17.4 User Program Mode (example)540................................................................................................................................................................
Boot Mode541................................................................................................................................................................
Figure 17.6 Boot Mode Execution Procedure542................................................................................................................................................................
Figure 17.7 Measurement Of Low Period Of Host's Transmit Data543................................................................................................................................................................
Figure 17.8 Ram Areas In Boot Mode544................................................................................................................................................................
User Program Mode546................................................................................................................................................................
Figure 17.9 User Program Mode Execution Procedure (example)547................................................................................................................................................................
Flash Memory Programming/erasing548................................................................................................................................................................
Program Mode549................................................................................................................................................................
Program-verify Mode550................................................................................................................................................................
Figure 17.11 Program/program-verify Flowchart (32-byte Programming)551................................................................................................................................................................
Erase Mode552................................................................................................................................................................
Figure 17.12 Erase/erase-verify Flowchart (single-block Erasing)553................................................................................................................................................................
Flash Memory Protection554................................................................................................................................................................
Software Protection556................................................................................................................................................................
Nmi Input Disabling Conditions558................................................................................................................................................................
Flash Memory Emulation In Ram559................................................................................................................................................................
Flash Memory Prom Mode561................................................................................................................................................................
Notes On Use Of Prom Mode562................................................................................................................................................................
Flash Memory Programming And Erasing Precautions563................................................................................................................................................................
Figure 17.16 Power-on/off Timing (boot Mode)565................................................................................................................................................................
Figure 17.17 Power-on/off Timing (user Program Mode)566................................................................................................................................................................
Mask Rom (h8/3062 Mask Rom Version, H8/3061 Mask Rom Version H8/3060 Mask Rom Version) Overview568................................................................................................................................................................
Notes On Ordering Mask Rom Version Chips569................................................................................................................................................................
Notes When Converting The F-ztat Application Software To The Mask-rom Versions570................................................................................................................................................................
H8/3064 Mask Rom B-mask Version]571................................................................................................................................................................
Differences From H8/3062f-ztat And H8/3062f-ztat R-mask Version572................................................................................................................................................................
Features573................................................................................................................................................................
Flash Memory Control Register 2 (flmcr2)579................................................................................................................................................................
Erase Block Register 1 (ebr1)580................................................................................................................................................................
Table 18.6 Flash Memory Area Divisions582................................................................................................................................................................
Overview Of Operation583................................................................................................................................................................
Figure 18.2 Flash Memory Related State Transitions584................................................................................................................................................................
On-board Programming Modes585................................................................................................................................................................
Block Configuration588................................................................................................................................................................
Figure 18.6 Boot Mode Execution Procedure591................................................................................................................................................................
Table 18.8 System Clock Frequencies For Which Automatic Adjustment Of H8/3064f-ztat B-mask Version Bit Rate Is Possible592................................................................................................................................................................
Figure 18.7 Ram Areas In Boot Mode593................................................................................................................................................................
Figure 18.8 Example Of User Program Mode Execution Procedure596................................................................................................................................................................
Figure 18.9 Flmcr1 Bit Settings And State Transitions598................................................................................................................................................................
Figure 18.10 Program/program-verify Flowchart (128-byte Programming)603................................................................................................................................................................
Figure 18.11 Erase/erase-verify Flowchart (single-block Erasing)605................................................................................................................................................................
Figure 18.14 Example Of Ram Overlap Operation611................................................................................................................................................................
Figure 18.16 Power-on/off Timing (boot Mode)617................................................................................................................................................................
Figure 18.17 Power-on/off Timing (user Program Mode)618................................................................................................................................................................
Mask Rom (h8/3064 Mask Rom B-mask Version) Overview620................................................................................................................................................................
Notes When Converting The F-ztat Application Software To The Mask-rom Version622................................................................................................................................................................
Of H8/3062, H8/3061, And H8/3060]623................................................................................................................................................................
Figure 19.2 Example Of Rom Area/ram Area Overlap634................................................................................................................................................................
Figure 19.3 Flash Memory Related State Transitions636................................................................................................................................................................
Figure 19.7 Boot Mode Execution Procedure643................................................................................................................................................................
Table 19.8 System Clock Frequencies For Which Automatic Adjustment Of H8/3062f-ztat B-mask Version Bit Rate Is Possible644................................................................................................................................................................
Figure 19.8 Ram Areas In Boot Mode645................................................................................................................................................................
Figure 19.9 Example Of User Program Mode Execution Procedure648................................................................................................................................................................
Figure 19.10 Flmcr1 Bit Settings And State Transitions650................................................................................................................................................................
Figure 19.11 Program/program-verify Flowchart (128-byte Programming)655................................................................................................................................................................
Figure 19.12 Erase/erase-verify Flowchart (single-block Erasing)657................................................................................................................................................................
Figure 19.16 Power-on/off Timing (boot Mode)669................................................................................................................................................................
Figure 19.17 Power-on/off Timing (user Program Mode)670................................................................................................................................................................
Mask Rom (h8/3062 Mask Rom B-mask Version, H8/3061 Mask Rom B-mask Version, H8/3060 Mask Rom B-mask Version) Overview672................................................................................................................................................................
Section 20 Clock Pulse Generator675................................................................................................................................................................
Oscillator Circuit676................................................................................................................................................................
Figure 20.3 Crystal Resonator Equivalent Circuit677................................................................................................................................................................
External Clock Input678................................................................................................................................................................
Table 20.3 (1) Clock Timing For On-chip Flash Memory Versions679................................................................................................................................................................
Duty Adjustment Circuit680................................................................................................................................................................
Section 21 Power-down State683................................................................................................................................................................
Table 21.1 Power-down State And Module Standby Function684................................................................................................................................................................
Module Standby Control Register H (mstcrh)687................................................................................................................................................................
Module Standby Control Register L (mstcrl)688................................................................................................................................................................
Sleep Mode690................................................................................................................................................................
Exit From Software Standby Mode691................................................................................................................................................................
Table 21.3 Clock Frequency And Waiting Time For Clock To Settle692................................................................................................................................................................
Sample Application Of Software Standby Mode693................................................................................................................................................................
Cautions On Clearing The Software Standby Mode Of F-ztat Version694................................................................................................................................................................
Hardware Standby Mode695................................................................................................................................................................
Module Standby Function696................................................................................................................................................................
System Clock Output Disabling Function697................................................................................................................................................................
Section 22 Electrical Characteristics699................................................................................................................................................................
Electrical Characteristics Of H8/3062 Mask Rom Version, H8/3061 Mask Rom Version And H8/3060 Mask Rom Version700................................................................................................................................................................
Dc Characteristics701................................................................................................................................................................
Table 22.3 Dc Characteristics (2)704................................................................................................................................................................
Table 22.3 Dc Characteristics (3)707................................................................................................................................................................
Figure 22.1 Darlington Pair Drive Circuit (example)710................................................................................................................................................................
Figure 22.2 Sample Led Circuit711................................................................................................................................................................
Ac Characteristics712................................................................................................................................................................
Table 22.6 Control Signal Timing713................................................................................................................................................................
Table 22.7 Bus Timing714................................................................................................................................................................
Table 22.8 Timing Of On-chip Supporting Modules716................................................................................................................................................................
Figure 22.3 Output Load Circuit717................................................................................................................................................................
A/d Conversion Characteristics718................................................................................................................................................................
D/a Conversion Characteristics720................................................................................................................................................................
Electrical Characteristics Of H8/3062f-ztat And H8/3062f-ztat R-mask Version721................................................................................................................................................................
Table 22.12 Dc Characteristics (2)725................................................................................................................................................................
Figure 22.4 Darlington Pair Drive Circuit (example)728................................................................................................................................................................
Figure 22.5 Sample Led Circuit729................................................................................................................................................................
Table 22.15 Control Signal Timing731................................................................................................................................................................
Table 22.16 Bus Timing732................................................................................................................................................................
Table 22.17 Timing Of On-chip Supporting Modules734................................................................................................................................................................
Figure 22.6 Output Load Circuit735................................................................................................................................................................
Flash Memory Characteristics739................................................................................................................................................................
Table 22.20 Flash Memory Characteristics (2)741................................................................................................................................................................
Electrical Characteristics Of H8/3064f-ztat B-mask Version743................................................................................................................................................................
Figure 22.7 Darlington Pair Drive Circuit (example)747................................................................................................................................................................
Figure 22.8 Sample Led Circuit748................................................................................................................................................................
Table 22.25 Control Signal Timing750................................................................................................................................................................
Table 22.26 Bus Timing751................................................................................................................................................................
Table 22.27 Timing Of On-chip Supporting Modules753................................................................................................................................................................
Figure 22.9 Output Load Circuit754................................................................................................................................................................
Electrical Characteristics Of H8/3064 Mask Rom B-mask Version759................................................................................................................................................................
Table 22.33 Permissible Output Currents762................................................................................................................................................................
Figure 22.10 Darlington Pair Drive Circuit (example)763................................................................................................................................................................
Table 22.35 Control Signal Timing765................................................................................................................................................................
Table 22.36 Bus Timing766................................................................................................................................................................
Table 22.37 Timing Of On-chip Supporting Modules768................................................................................................................................................................
Figure 22.12 Output Load Circuit769................................................................................................................................................................
Electrical Characteristics Of H8/3062f-ztat B-mask Version772................................................................................................................................................................
Figure 22.13 Darlington Pair Drive Circuit (example)776................................................................................................................................................................
Figure 22.14 Sample Led Circuit777................................................................................................................................................................
Table 22.44 Control Signal Timing779................................................................................................................................................................
Table 22.45 Bus Timing780................................................................................................................................................................
Table 22.46 Timing Of On-chip Supporting Modules782................................................................................................................................................................
Figure 22.15 Output Load Circuit783................................................................................................................................................................
Electrical Characteristics Of H8/3062 Mask Rom B-mask Version H8/3061 Mask Rom B-mask Version, And H8/3060 Mask Rom B-mask Version788................................................................................................................................................................
Table 22.52 Permissible Output Currents791................................................................................................................................................................
Figure 22.16 Darlington Pair Drive Circuit (example)792................................................................................................................................................................
Table 22.54 Control Signal Timing794................................................................................................................................................................
Table 22.55 Bus Timing795................................................................................................................................................................
Table 22.56 Timing Of On-chip Supporting Modules797................................................................................................................................................................
Figure 22.18 Output Load Circuit798................................................................................................................................................................
Operational Timing801................................................................................................................................................................
Control Signal Timing802................................................................................................................................................................
Figure 22.22 Interrupt Input Timing803................................................................................................................................................................
Bus Timing804................................................................................................................................................................
Figure 22.23 Basic Bus Cycle: Two-state Access805................................................................................................................................................................
Figure 22.24 Basic Bus Cycle: Three-state Access806................................................................................................................................................................
Figure 22.25 Basic Bus Cycle: Three-state Access With One Wait State807................................................................................................................................................................
Tpc And I/o Port Timing808................................................................................................................................................................
Sci Input/output Timing809................................................................................................................................................................
Appendix A Instruction Set811................................................................................................................................................................
Table A.1 Instruction Set813................................................................................................................................................................
Arithmetic Instructions815................................................................................................................................................................
Bit Manipulation Instructions820................................................................................................................................................................
A.2 Operation Code Maps826................................................................................................................................................................
Table A.2 Operation Code Map (2)827................................................................................................................................................................
Table A.2 Operation Code Map (3)828................................................................................................................................................................
A.3 Number Of States Required For Execution829................................................................................................................................................................
Table A.3 Number Of States Per Cycle830................................................................................................................................................................
Table A.4 Number Of Cycles Per Instruction831................................................................................................................................................................
Appendix B Internal I/o Registers838................................................................................................................................................................
B.4 Functions869................................................................................................................................................................
Flash Memory889................................................................................................................................................................
Appendix C I/o Port Block Diagrams944................................................................................................................................................................
C.2 Port 2 Block Diagram945................................................................................................................................................................
C.3 Port 3 Block Diagram946................................................................................................................................................................
C.4 Port 4 Block Diagram947................................................................................................................................................................
C.5 Port 5 Block Diagram948................................................................................................................................................................
C.6 Port 6 Block Diagrams949................................................................................................................................................................
Figure C.6 (e) Port 6 Block Diagram (pin P6 7 )953................................................................................................................................................................
C.7 Port 7 Block Diagrams954................................................................................................................................................................
C.8 Port 8 Block Diagrams955................................................................................................................................................................
C.9 Port 9 Block Diagrams959................................................................................................................................................................
Figure C.9 (e) Port 9 Block Diagram (pin P9 )963................................................................................................................................................................
C.10 Port A Block Diagrams965................................................................................................................................................................
C.11 Port B Block Diagrams968................................................................................................................................................................
Appendix D Pin States974................................................................................................................................................................
D.2 Pin States At Reset978................................................................................................................................................................
Figure D.2 Reset During Memory Access (modes 3 And 4)979................................................................................................................................................................
Figure D.3 Reset During Memory Access (mode 5)980................................................................................................................................................................
Appendix F Product Code Lineup982................................................................................................................................................................
Appendix G Package Dimensions984................................................................................................................................................................
Figure G.2 Package Dimensions (tfp-100b)985................................................................................................................................................................
Figure G.3 Package Dimensions (fp-100a)986................................................................................................................................................................
H.1 Differences Between H8/3067 And H8/3062 Series, H8/3048 Series H8/3007 And H8/3006, And H8/3002987................................................................................................................................................................
H.2 Comparison Of Pin Functions Of 100-pin Package Products (fp-100b, Tfp-100b)990................................................................................................................................................................

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Hitachi H8/3060 Hardware Manual

Hitachi H8/3060 Hardware Manual (939 pages)

Single-Chip Microcomputer  
Brand: Hitachi | Category: Computer Hardware | Size: 2.98 MB
Table of contents
Section 1 Overview26................................................................................................................................................................
Pin Description32................................................................................................................................................................
Address Space54................................................................................................................................................................
Data Formats59................................................................................................................................................................
Instruction Set62................................................................................................................................................................
Processing States82................................................................................................................................................................
Interrupt Sources128................................................................................................................................................................
Overview Of Flash Memory493................................................................................................................................................................
Boot Mode504................................................................................................................................................................
User Program Mode505................................................................................................................................................................
Oscillator Circuit636................................................................................................................................................................
Sleep Mode650................................................................................................................................................................
Data Transfer Instructions758................................................................................................................................................................
Arithmetic Instructions760................................................................................................................................................................
Bit Manipulation Instructions765................................................................................................................................................................
Flash Memory834................................................................................................................................................................
Specifications932................................................................................................................................................................

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