Block Diagram - Hitachi H8S/2678 Series Reference Manual

6.16 Clock Pulse Generator
6.16.1 Features
• Comprises an oscillator, PLL (phase-locked loop) circuit, and frequency divider
• Generates system clock (ø) and internal clock
6.16.2

Block Diagram

EXTAL
Oscillator
XTAL
PLLCR
STC0, STC1
PLL circuit
(×1, ×2, ×4)
Figure 6.17 Block Diagram of Clock Pulse Generator
SCKCR
SCK2 to SCK0
Frequency
divider
System clock
To ø pin
Internal clock
To on-chip
supporting
modules
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