Hitachi H8S/2678 Series Reference Manual page 612

16-bit single-chip microcomputer
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SSR2—Serial Status Register 2
Bit
TDRE
Initial value
Read/Write
R/(W)*
Transmit Data Register Empty
Note: * Can only be written with 0, to clear the flag.
7
6
RDRF
ORER
1
0
R/(W)*
R/(W)*
Receive Data Register Full
0 [Clearing conditions]
• When 0 is written to RDRF after reading RDRF = 1
• When the DMAC or DTC is activated by an RXI interrupt and reads data from RDR
1
[Setting condition]
When serial reception ends normally and receive data is transferred from RSR to RDR
0 [Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DMAC or DTC is activated by a TXI interrupt and writes data to TDR
1
[Setting conditions]
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and data can be written to TDR
H'FF8C
5
4
FER
PER
0
0
R/(W)*
R/(W)*
Transmit End
0 [Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DMAC or DTC is activated by a TXI
1
[Setting conditions]
• When the TE bit in SCR is 0
• When TDRE = 1 at transmission of the last bit of
Parity Error
0 [Clearing condition]
When 0 is written to PER after reading PER = 1
1
[Setting condition]
When, in reception, the number of 1 bits in the receive
data plus the parity bit does not match the parity setting
(even or odd) specified by the O/E bit in SMR
Framing Error
0 [Clearing condition]
When 0 is written to FER after reading FER = 1
1
[Setting condition]
When the SCI checks the stop bit at the end of the receive data
when reception ends, and the stop bit is 0
Overrun Error
0 [Clearing condition]
When 0 is written to ORER after reading ORER = 1
1
[Setting condition]
When the next serial reception is completed while RDRF = 1
3
2
TEND
MPB
0
1
R
Multiprocessor Bit Transfer
0 Data with a 0 multiprocessor
bit is transmitted
1
Data with a 1 multiprocessor
bit is transmitted
Multiprocessor Bit
0 [Clearing condition]
When data with a 0 multiprocessor bit is received
1
[Setting condition]
When data with a 1 multiprocessor bit is received
interrupt and writes data to TDR
a 1-byte serial transmit character
SCI2
1
0
MPBT
0
0
R
R/W
595

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