Hitachi H8S/2678 Series Reference Manual page 418

ø
A23 to A0
RAS5 to RAS2
UCAS
LCAS
OE, RD
HWR
Read
D15 to D0
OE, RD
HWR
Write
D15 to D0
AS
DACK0, DACK1
EDACK0 to EDACK3
Note: DACK and EDACK timing: when DDS = 0 and EDDS = 0
RAS timing: when RAST = 1
Figure 7.16 DRAM Access Timing: Three-State Access (RAST = 1)
Tp Tr
t
AD
t t
AS2 AH2
t
CSD2
t
PCH1
Tc1 Tc2
t
AD
t
AS3
t
OED2
t
AA5
t
AC7
t
t
WCS2
WRD2
t
WDD
t
WDS2
t
DACD1
t
EDACD1
Tc3
t
CSD3
t
AH3
t
CASD1
t
CASD2
t
CASW2
t
t
OED1
AC2
t
t
RDS2
RDH2
t
WCH2
t
WRD2
t
WDH3
t
DACD2
t
EDACD2
401