Hitachi H8S/2678 Series Reference Manual page 180

Full access Burst access
T T T T T T T
1 2 3 1 2 1 2
ø
Upper
address bus
Lower
address bus
CSn
AS
RD
Data bus
Note: n = 1 or 0
Figure 4.42 Example of Burst ROM Access Timing (1)
(ASTn = 1, 2-State Burst Cycle)
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