Hitachi H8S/2678 Series Reference Manual page 556

DMACR0A—DMA Control Register 0A
DMACR1A—DMA Control Register 1A
DMACR0B—DMA Control Register 0B
DMACR1B—DMA Control Register 1B
Full address mode
DMACRA
15
Bit
DTSZ
DMACRA
0
Initial value
R/W
Read/Write
Data Transfer Size
0
1
14 13
SAID SAIDE
0 0
R/W R/W
Source Address Increment/Decrement
0 0 MARA is fixed
1 MARA is incremented after a data transfer
(1) When DTSZ = 0, MARA is incremented by 1 after a transfer
(2) When DTSZ = 1, MARA is incremented by 2 after a transfer
1 0 MARA is fixed
1 MARA is decremented after a data transfer
(1) When DTSZ = 0, MARA is decremented by 1 after a transfer
(2) When DTSZ = 1, MARA is decremented by 2 after a transfer
Byte-size transfer
Word-size transfer
H'FF22
H'FF24
H'FF23
H'FF25
12 11
BLKDIR BLKE
0 0
R/W R/W
Block Direction/Block Enable
0 0 Transfer in normal mode
1 Transfer in block transfer mode,
destination is block area
1 0 Transfer in normal mode
1 Transfer in block transfer mode,
source is block area
10 9
— —
0 0
R/W R/W
DMAC
DMAC
DMAC
DMAC
8
—
0
R/W
539