Block Diagram - Hitachi H8S/2678 Series Reference Manual

1. Interrupt request to CPU
2. Activation request to DTC
3. Activation request to DMAC
4. Selection of a number of the above
For details of interrupt requests that can be used to activate the DTC or DMAC, see section 6,
Data Transfer Controller, and section 5, DMA Controller, in the H8S/2678 Series Hardware
Manual.
3.7.2

Block Diagram

Figure 3.9 shows a block diagram of the DTC, DMAC, and interrupt controller.
IRQ
interrupt
Interrupt source
On-chip
clear signal
supporting
module
86
Disable
signal
Interrupt
request
Selection
circuit
Select
signal
DTCER
DTVECR
Interrupt controller
Figure 3.9 Interrupt Control for DTC and DMAC
DMAC
Clear
Control logic
signal
SWDTE
clear signal
Priority
determination
Clear
signal
DTC activation
request vector
number
Clear signal
CPU interrupt
request vector
number
I, I2 to I0
DTC
CPU