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Full address mode
DMACRB
Bit
DMACRB
Initial value
Read/Write
Data Transfer Factor
DTF3 DTF2 DTF1 DTF0
Destination Address Increment/Decrement
0
0
MARB is fixed
1
MARB is incremented after a data transfer
(1) When DTSZ = 0, MARB is incremented by 1 after a transfer
(2) When DTSZ = 1, MARB is incremented by 2 after a transfer
1
0
MARB is fixed
1
MARB is decremented after a data transfer
(1) When DTSZ = 0, MARB is decremented by 1 after a transfer
(2) When DTSZ = 1, MARB is decremented by 2 after a transfer
540
7
6
—
DAID
DAIDE
0
0
R/W
R/W
R/W
0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
1
1
0
1
5
4
3
—
DTF3
0
0
0
R/W
R/W
Block Transfer Mode
—
A/D converter conversion end
interrupt
DREQ pin falling edge input
DREQ pin low-level input
SCI channel 0 transmission
complete interrupt
SCI channel 0 reception
complete interrupt
SCI channel 1 transmission
complete interrupt
SCI channel 1 reception
complete interrupt
TPU channel 0 compare match/
input capture A interrupt
TPU channel 1 compare match/
input capture A interrupt
TPU channel 2 compare match/
input capture A interrupt
TPU channel 3 compare match/
input capture A interrupt
TPU channel 4 compare match/
input capture A interrupt
TPU channel 5 compare match/
input capture A interrupt
—
—
2
1
DTF2
DTF1
DTF0
0
0
R/W
R/W
R/W
Normal Mode
—
—
DREQ pin falling edge input
DREQ pin low-level input
—
—
Auto-request (cycle steal)
Auto-request (burst)
—
—
—
—
—
—
—
—
*: Don't care
0
0
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