Hitachi H8S/2678 Series Reference Manual page 481

EDMDR0—EXDMA Mode Control Register 0
Bit 15
EDA
0
Initial value
R/(W)
Read/Write
EXDMA Active
0
1
Notes: 1. The value written in bit EDA may not be effective immediately.
2. Bit BEF can only be written with 0 after being read as 1, to clear the flag.
464
14 13
BEF EDRAKE
0 0
*1 *2
R/(W) R/W
EDRAK Pin Output Enable
0
1
Block Transfer Error Flag
0 No block transfer error
[Clearing condition]
Writing 0 to BEF after reading BEF = 1
1 Block transfer error
[Setting condition]
NMI interrupt during block transfer
Data transfer disabled on corresponding channel
[Clearing conditions]
• When the specified number of transfers end
• When operation is halted by a repeat area overflow interrupt
• When 0 is written to EDA while EDA = 1
(In block transfer mode, write is effective after end of one-block transfer)
• Reset, NMI interrupt, or hardware standby mode
Data transfer enabled on corresponding channel. EXDMA operation in progress
H'FDCC
12 11
ETENDE EDREQS
0 0
R/W R/W
Address Mode Select
0
1
EDREQ Select
0 Low level sensing
1 Falling edge sensing
ETEND Pin Output Enable
ETEND pin output disabled
0
ETEND pin output enabled
1
EDRAK pin output disabled
EDRAK pin output enabled
10 9
AMS MDS1
0 0
R/W R/W
Mode Select 1 and 0
0 0 Auto request, cycle steal mode,
normal transfer mode
1 Auto request, burst mode,
normal transfer mode
1 0 External request, cycle steal mode,
normal transfer mode
1 External request, cycle steal mode,
block transfer mode
Dual address mode
Single address mode
EXDMAC
8
MDS0
0
R/W