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EDACR2—EXDMA Address Control Register 2
Bit
15
SAT1
0
Initial value
R/W
Read/Write
Source Address Repeat Area
0
0
0
0
0
:
1
1
1
1
1
1
*: Don't care
Source Address Repeat Interrupt Enable
0
Source address repeat interrupt is not requested
1
When source address repeat area overflow occurs, the IRF bit
in EDMDR is set to 1 and an interrupt is requested
Source Address Update Mode
0
Source address (EDSAR) is fixed
*
1
0
Source address is incremented (+1 in byte transfer, +2 in word transfer)
1
Source address is decremented (–1 in byte transfer, –2 in word transfer)
*: Don't care
478
14
13
SAT0
SARIE
0
0
R/W
R/W
0
0
0
0
Source address (EDSAR) is not designated as repeat area
0
0
0
1
Lower 1 bit of EDSAR (2-byte area) designated as repeat area
0
0
1
0
Lower 2 bits of EDSAR (4-byte area) designated as repeat area
0
0
1
1
Lower 3 bits of EDSAR (8-byte area) designated as repeat area
0
1
0
0
Lower 4 bits of EDSAR (16-byte area) designated as repeat area
:
:
:
:
: (Continues in the same way)
0
0
1
1
Lower 19 bits of EDSAR (512-kbyte area) designated as repeat area
0
1
0
0
Lower 20 bits of EDSAR (1-Mbyte area) designated as repeat area
0
1
0
1
Lower 21 bits of EDSAR (2-Mbyte area) designated as repeat area
0
1
1
0
Lower 22 bits of EDSAR (4-Mbyte area) designated as repeat area
0
1
1
1
Lower 23 bits of EDSAR (8-Mbyte area) designated as repeat area
1
*
*
*
Reserved (setting prohibited)
H'FDEE
12
11
SARA4
SARA3
0
0
R/W
R/W
10
9
SARA2
SARA1
0
0
R/W
R/W
EXDMAC
8
SARA0
0
R/W
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