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4.5.9
Precharge State Control
When DRAM is accessed, a RAS precharge time must be secured. With the H8S/2678 Series, one
T
state is always inserted when DRAM space is accessed. From one to four T
p
selected by setting bits TPC1 and TPC0 in DRACCR. Set the optimum number of T
according to the DRAM connected and the operating frequency of the chip. Figure 4.24 shows the
timing when two Tp states are inserted.
The setting of bits TPC1 and TPC0 is also valid for T
ø
Address bus
RASn (CSn)
UCAS, LCAS
WE (HWR)
OE (RD)
Read
Data bus
WE (HWR)
Write
OE (RD)
Data bus
Note: n = 2 to 5
Figure 4.24 Example of Timing with Two-State Precharge Cycle
T
T
p1
p2
Row address
(RAST = 0, CAST = 0)
states in refresh cycles.
p
T
T
r
c1
Column address
High
High
states can be
p
cycles
p
T
c2
145
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