Hitachi H8S/2678 Series Reference Manual page 97

16-bit single-chip microcomputer
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Level 7 interrupt?
Mask level 6
or below?
Figure 3.6 Flowchart of Procedure Up to Interrupt Acceptance
80
Program execution state
Yes
No
Yes
Level 6 interrupt?
No
Yes
Mask level 5
Save PC, CCR, and EXR
Clear T bit to 0
Update mask level
Read vector address
Branch to interrupt
service routine
in Interrupt Control Mode 2
No
Interrupt
generated?
Yes
NMI?
No
No
Yes
No
or below?
Yes
Level 1 interrupt?
Yes
Mask level 0?
Yes
Hold pending
No
No

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