Cs Assertion Period Control Registers (Csacrh, Csacrl) - Hitachi H8S/2678 Series Reference Manual

CS Assertion Period Control Registers (CSACRH, CSACRL)

4.2.5
CSACRH
Bit 7
CSXH7
Initial value 0
Read/Write R/W
CSACRL
Bit 7
CSXT7
Initial value 0
Read/Write R/W
CSACRH and CSACRL are 8-bit readable/writable registers that specify whether or not the
assertion period of the basic bus interface chip select signals (CSn) and address signals is to be
extended.
Extending the assertion period of the CSn and address signals allows flexible interfacing to
external I/O devices.
CSACRH and CSACRL are initialized to H'0000 by a reset and in hardware standby mode. They
are not initialized in software standby mode.
6 5
CSXH6 CSXH5
0 0
R/W R/W
6 5
CSXT6 CSXT5
0 0
R/W R/W
4 3
CSXH4 CSXH3
0 0
R/W R/W
4 3
CSXT4 CSXT3
0 0
R/W R/W
2 1
CSXH2 CSXH1
0 0
R/W R/W
2 1
CSXT2 CSXT1
0 0
R/W R/W
0
CSXH0
0
R/W
0
CSXT0
0
R/W
101