Hitachi H8S/2678 Series Reference Manual page 123

16-bit single-chip microcomputer

Table of Contents

when an internal bus master performs an external space access, or when a refresh request is

BREQO output disabled

BREQO pin can be used as I/O port

BREQO output enabled

Bit 13—Reserved: This is a readable/writable bit, but the write value should always be 0.

Bit 12—Idle Cycle State Number Select (IDLC): Selects the number of states in the idle cycle

set by ICIS1 and ICIS0.

Idle cycle comprises 1 state

Idle cycle comprises 2 states

Bit 11—Idle Cycle Insert 1 (ICIS1): When consecutive external read cycles are performed in

different areas, an idle cycle can be inserted between the bus cycles. When this bit is set to 1, an

idle cycle is inserted in the case of consecutive external read cycles in different areas.

Idle cycle not inserted in case of consecutive external read cycles in different areas

Idle cycle inserted in case of consecutive external read cycles in different areas

Bit 10—Idle Cycle Insert 0 (ICIS0): When an external read cycle and external write cycle are

performed consecutively, an idle cycle can be inserted between the bus cycles. When this bit is set

to 1, an idle cycle is inserted when an external read cycle and external write cycle are performed

consecutively.

Idle cycle not inserted when external read cycle and external write cycle are

performed consecutively

Idle cycle inserted when external read cycle and external write cycle are performed

consecutively

(Initial value)