Hitachi H8S/2678 Series Reference Manual page 161

If a row address hold time or read access time is necessary, making a setting in bits RCD1 and
RCD0 in the DRACCR register allows from one to three T
maintained, to be inserted between the T
cycle, in which the column address is output. Use the setting that gives the optimum row address
signal hold time relative to the fall of the RAS signal according to the DRAM connected and the
operating frequency of the chip. Figure 4.23 shows an example of the timing when one T
set.
ø
Address bus
RASn (CSn)
UCAS, LCAS
WE (HWR)
Read OE (RD)
Data bus
WE (HWR)
Write
OE (RD)
Data bus
Note: n = 2 to 5
Figure 4.23 Example of Timing with One Row Address Output Maintenance State
144
cycle, in which the RAS signal goes low, and the T
r
T T
p r
Row address
(RAST = 0, CAST = 0)
states, in which row address output is
rw
T T
rw c1
Column address
High
High
c1
state is
rw
T
c2