Hitachi H8S/2678 Series Reference Manual page 616

ADCSR—A/D Control/Status Register
Bit
ADF
Initial value
R/W *
Read/Write
A/D End Flag
0
1
Note: * Can only be written with 0, to clear the flag.
7 6
ADIE ADST
0 0
R/W R/W
A/D Start
0
1
A/D Interrupt Enable
0 A/D conversion end interrupt request disabled
1 A/D conversion end interrupt request enabled
[Clearing conditions]
• When 0 is written to ADF after reading ADF = 1
• When the DTC is activated by an ADF interrupt and ADDR is read
[Setting conditions]
• Single mode: When A/D conversion ends
• Scan mode: When A/D conversion ends on all specified channels
5 4
SCAN CKS
0 0
R/W R/W
Clock Select
Note: CKS is used in combination with
Scan Mode
0 Single mode
1 Scan mode
A/D conversion stopped
• Single mode: A/D conversion is started; cleared to 0
automatically when conversion ends
• Scan mode: A/D conversion is started, and continues
consecutively on the selected channels until ADST is
cleared to 0 by software, a reset, or a transition to
standby mode or module stop mode
H'FF98
3 2
CH2 CH1
0 0
R/W
Channel Select
Note: CH2, CH1, and CH0 are
used in combination with
bit 2 (CH3) in ADCR. See
ADCR—A/D Control
Register (H'FF99) for
details.
bit 3 (CKS1) in ADCR. See
ADCR—A/D Control Register
(H'FF99) for details.
A/D Converter
1 0
CH0
0 0
R/W R/W
599