Hitachi H8S/2678 Series Reference Manual page 288

Port E Data Register (PEDR)
Bit 7
PE7DR
Initial value 0
Read/Write R/W
PEDR is an 8-bit readable/writable register that stores output data for the port E pins (PE7 to PE0).
PEDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
Port E Register (PORTE)
Bit 7
PE7
Initial value —*
Read/Write R
Note: * Determined by the state of pins PE7 to PE0.
PORTE is an 8-bit read-only register that shows the pin states. PORTE cannot be written to;
writing of output data for the port E pins (PE7 to PE0) must always be performed on PEDR.
If a port E read is performed while PEDDR bits are set to 1, the PEDR values are read. If a port E
read is performed while PEDDR bits are cleared to 0, the pin states are read.
After a reset and in hardware standby mode, PORTE contents are determined by the pin states, as
PEDDR and PEDR are initialized. PORTE retains its prior state in software standby mode.
Port E MOS Pull-Up Control Register (PEPCR)
Bit 7
PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR
Initial value 0
Read/Write R/W
PEPCR is an 8-bit readable/writable register that controls the MOS input pull-up function
incorporated into port E on a bit-by-bit basis.
In 8-bit bus mode, when a PEDDR bit is cleared to 0 (input port setting), setting the corresponding
PEPCR bit to 1 turns on the MOS input pull-up for the corresponding pin.
6 5
PE6DR PE5DR
0 0
R/W R/W
6 5
PE6 PE5
—* —*
R R
6 5
0 0
R/W R/W
4 3
PE4DR PE3DR
0 0
R/W R/W
4 3
PE4 PE3
—* —*
R R
4 3
0 0
R/W R/W
2 1
PE2DR PE1DR
0 0
R/W R/W
2 1
PE2 PE1
—* —*
R R
2 1
0 0
R/W R/W
0
PE0DR
0
R/W
0
PE0
—*
R
0
0
R/W
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