Hitachi H8S/2678 Series Reference Manual page 133

Bit 3—Self-Refresh Enable (SLFRF): If this bit is set to 1, DRAM self-refresh mode is selected
when a transition is made to the software standby state.
This bit is valid when the RFSHE bit is set to 1, enabling refresh operations. It is cleared after
recovery from software standby mode.
Bit 3
SLFRF Description
0 Self-refreshing is disabled in software standby mode
1 Self-refreshing is enabled in software standby mode
Bits 2 to 0—Self-Refresh Precharge Cycle Control (TPCS2 to TPCS0): These bits select the
number of states in the precharge cycle immediately after self-refreshing.
The number of states in the precharge cycle immediately after self-refreshing are added to the
number of states set by bits TPC1 and TPC0 in the DRACCR register.
Bit 2 Bit 1
TPCS2 TPCS1
0 0
1
1 0
1
116
Bit 0
TPCS0 Description
RAS precharge cycle after self-refresh =
0
[TPC set value] states
RAS precharge cycle after self-refresh =
1
[TPC set value + 1] states
RAS precharge cycle after self-refresh =
0
[TPC set value + 2] states
RAS precharge cycle after self-refresh =
1
[TPC set value + 3] states
RAS precharge cycle after self-refresh =
0
[TPC set value + 4] states
RAS precharge cycle after self-refresh =
1
[TPC set value + 5] states
RAS precharge cycle after self-refresh =
0
[TPC set value + 6] states
RAS precharge cycle after self-refresh =
1
[TPC set value + 7] states
(Initial value)
(Initial value)