Hitachi H8S/2678 Series Reference Manual page 306

Port H Data Register (PHDR)
Bit 7
—
Initial value 0
Read/Write —
PHDR is a 4-bit readable/writable register that stores output data for the port H pins (PH3 to PH0).
Bits 7 to 4 are reserved; they are always read as 0 and cannot be modified.
PHDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
Port H Register (PORTH)
Bit 7
—
Initial value
Undefined Undefined Undefined Undefined
Read/Write —
Note: * Determined by the state of pins PH3 to PH0.
PORTH is a 4-bit read-only register that shows the pin states. PORTH cannot be written to;
writing of output data for the port H pins (PH3 to PH0) must always be performed on PHDR.
Bits 7 to 4 are reserved; if read they will return an undefined value.
If a port H read is performed while PHDDR bits are set to 1, the PHDR values are read. If a port H
read is performed while PHDDR bits are cleared to 0, the pin states are read.
After a reset and in hardware standby mode, PORTH contents are determined by the pin states, as
PHDDR and PHDR are initialized. PORTH retains its prior state in software standby mode.
Port Function Control Register 0 (PFCR0)
Bit 7
CS7E
Initial value 1
Read/Write R/W
PFCR0 is an 8-bit readable/writable register that performs I/O port control. PFCR0 is initialized to
H'FF by a reset and in hardware standby mode. It retains its prior state in software standby mode.
6 5
— —
0 0
— —
6 5
— —
— —
6 5
CS6E CS5E
1 1
R/W R/W
4 3
— PH3DR
0 0
— R/W
4 3
— PH3
—*
— R
4 3
CS4E CS3E
1 1
R/W R/W
2 1
PH2DR PH1DR
0 0
R/W R/W
2 1
PH2 PH1
—* —*
R R
2 1
CS2E CS1E
1 1
R/W R/W
0
PH0DR
0
R/W
0
PH0
—*
R
0
CS0E
1
R/W
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