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Interrupt Source
TGI3A (TGR3A compare
match/input capture)
TGI3B (TGR3B compare
match/input capture)
TGI3C (TGR3C compare
match/input capture)
TGI3D (TGR3D compare
match/input capture)
TGI4A (TGR4A compare
match/input capture)
TGI4B (TGR4B compare
match/input capture)
TGI5A (TGR5A compare
match/input capture)
TGI5B (TGR5B compare
match/input capture)
CMI0A (compare match A)
CMI0B (compare match B)
CMI1A (compare match A)
CMI1B (compare match B)
DMTEND0A (channel 0/channel
0A transfer end)
DMTEND0B (channel 0B transfer
end)
DMTEND1A (channel 1/channel
1A transfer end)
DMTEND1B (channel 1B transfer
end)
RXI0 (receive completed 0)
TXI0 (transmit data empty 0)
RXI1 (receive completed 1)
TXI1 (transmit data empty 1)
RXI2 (receive completed 2)
TXI2 (transmit data empty 2)
Note: * DTCE bits with no corresponding interrupt are reserved, and should be written with 0.
When clearing the software standby state or all-module-clocks-stop mode with an interrupt,
write 0 to the corresponding DTCE bit.
Origin of
Interrupt
Vector
Source
Number
TPU
56
channel 3
57
58
59
TPU
64
channel 4
65
TPU
68
channel 5
69
8-bit timer
72
channel 0
73
8-bit timer
76
channel 1
77
DMAC
80
81
82
83
SCI channel 0
89
90
SCI channel 1
93
94
SCI channel 2
97
98
Vector Address
Advanced Mode
DTCE*
H'0470
DTCED5
H'0472
DTCED4
H'0474
DTCED3
H'0476
DTCED2
H'0480
DTCED1
H'0482
DTCED0
H'0488
DTCEE7
H'048A
DTCEE6
H'0490
DTCEE3
H'0492
DTCEE2
H'0498
DTCEE1
H'049A
DTCEE0
H'04A0
DTCEF7
H'04A2
DTCEF6
H'04A4
DTCEF5
H'04A6
DTCEF4
H'04B2
DTCEF3
H'04B4
DTCEF2
H'04BA
DTCEF1
H'04BC
DTCEF0
H'04C2
DTCEG7
H'04C4
DTCEG6
Priority
High
Low
89
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