Hitachi H8S/2678 Series Reference Manual page 144

8-Bit, 3-State Access Space: Figure 4.10 shows the bus timing for an 8-bit, 3-state access space.
When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used.
The LWR pin is fixed high. Wait states can be inserted.
ø
Address bus
CSn
AS
RD
D15 to D8
Read
D7 to D0
HWR
LWR
Write
D15 to D8
D7 to D0
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 4.10 Bus Timing for 8-Bit, 3-State Access Space
Bus cycle
T T
1 2
High
High impedance
T
3
Valid
Invalid
Valid
127