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3.5.5
Interrupt Response Times
The H8S/2678 Series is capable of fast word access to on-chip memory, and the program area is
provided in on-chip ROM and the stack area in on-chip RAM, enabling high-speed processing.
Table 3.10 shows interrupt response times—the interval between generation of an interrupt request
and execution of the first instruction in the interrupt service routine. The symbols used in table
3.10 are explained in table 3.11.
Table 3.10 Interrupt Response Times
No.
Item
1
Interrupt priority determination*
2
Number of wait states until executing
instruction ends*
3
Saving PC, CCR, EXR to stack
4
Vector fetch
5
Instruction fetch*
6
Internal processing*
Total (using on-chip memory)
Notes: 1. Two states in case of internal interrupt.
2. Refers to MULXS and DIVXS instructions.
3. Prefetch after interrupt acceptance and interrupt service routine prefetch.
4. Internal processing after interrupt acceptance and internal processing after vector fetch.
Table 3.11 Number of States in Interrupt Exception Handling
Symbol
Instruction fetch S
I
Branch address read S
Stack manipulation S
Legend
m: Number of wait states in an external device access
2
3
4
Internal
Memory
1
J
K
INTM1 = 0
1
3
1 to 19 + 2 ⋅ S
2 ⋅ S
K
2 ⋅ S
I
2 ⋅ S
I
2
12 to 32
Object of Access
8-Bit Bus
2-State
3-State
Access
Access
4
6 + 2m
Advanced Mode
INTM1 = 1
3
1 to 19 + 2 ⋅ S
I
3 ⋅ S
K
2 ⋅ S
I
2 ⋅ S
I
2
13 to 33
External Device
16-Bit Bus
2-State
Access
2
I
3-State
Access
3 + m
83
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