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TIOR0L—Timer I/O Control Register 0L
Bit
IOD3
Initial value
Read/Write
R/W
TGR0D I/O Control
0 0
1
Notes: 1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and ø/1 is used as the
Note: When TGRC or TGRD is designated for buffer operation, these settings are invalid and the register operates as a buffer
register.
614
7
6
IOD2
IOD1
0
0
R/W
R/W
TGR0C I/O Control
0 0
0 0
1
1 0
1
1 0 0
1
1 0
1
1
0
0 0 TGR0C
1
1 *
1
*
*
Note: When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer register,
this setting is invalid and input capture/output compare does not occur.
0 0
TGR0D
Output disabled
is output
1
Initial output is
compare
0 output
*2
register
1 0
1
1 0 0
Output disabled
1
Initial output is
1 output
1 0
1
0
0 0 TGR0D
Capture input
is input
source is
1
capture
TIOCD0 pin
*2
register
1 *
1
*
*
Capture input
source is channel
1/count clock
TCNT1 count clock, this setting is invalid and input capture does not occur.
2. When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register,
this setting is invalid and input capture does not occur.
H'FFD3
5
4
IOD0
IOC3
0
0
R/W
R/W
TGR0C
Output disabled
is output
Initial output is
compare
0 output
register
Output disabled
Initial output is
1 output
Capture input
is input
source is
capture
TIOCC0 pin
register
Capture input
source is channel
1/count clock
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at TCNT1 count-up/
count-down
3
2
IOC2
IOC1
0
0
R/W
R/W
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at TCNT1 count-up/
count-down
*1
*: Don't care
TPU0
1
0
IOC0
0
0
R/W
*: Don't care
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