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BCR—Bus Control Register
Bit
15
BRLE
Initial value
R/W
Read/Write
External Bus Release Enable
0
1
Bit
—
Initial value
Read/Write
R/W
14
BREQOE
0
0
R/W
R/W
Idle Cycle State Number Select
0
1
BREQO Pin Enable
BREQO signal output disabled
0
BREQO pin can be used as I/O port
BREQO signal output enabled
1
External bus release disabled
BREQ, BACK, and BREQO pins can be used as I/O ports
External bus release enabled
7
6
—
0
0
R/W
R/W
13
12
—
IDLC
ICIS1
0
1
R/W
R/W
Write Data Buffer Enable
0
Write data buffer function not used
1
Write data buffer function used
Idle Cycle Insert 0
0
Idle cycle not inserted when external read cycle and
external write cycle are performed consecutively
1
Idle cycle inserted when external read cycle and
external write cycle are performed consecutively
Idle Cycle Insert 1
0
Idle cycle not inserted in case of consecutive
external read cycles in different areas
1
Idle cycle inserted in case of consecutive
external read cycles in different areas
Idle cycle comprises 1 state
Idle cycle comprises 2 states
5
4
—
—
0
0
R/W
R/W
H'FECC
11
10
ICIS0
WDBE
1
1
R/W
R/W
WAIT Pin Enable
Wait input by WAIT pin disabled
0
WAIT pin can be used as I/O port
Wait input by WAIT pin enabled
1
3
2
—
—
0
0
R/W
R/W
Bus Controller
9
8
WAITE
0
0
R/W
1
0
—
—
0
0
R/W
523
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