Hitachi H8S/2678 Series Reference Manual page 563

16-bit single-chip microcomputer
Table of Contents

Advertisement

DTCER—DTC Enable Register
Bit
DTCE7
Initial value
Read/Write
R/W
Correspondence between Interrupt Sources and DTCER Register Bits
Register
7
DTCERA
IRQ0
DTCERB
IRQ8
DTCERC
DTCERD
TGI2A
DTCERE
TGI5A
DTCERF
DMTEND0A
DTCERG
RXI2
DTCERH
Note: For DTCE bit setting, bit manipulation instructions such as BSET and BCLR must be used
for reading and writing. For the initial setting only, however, when setting multiple
activation sources at one time, it is possible to disable interrupts and write to the relevant
register after a dummy read.
546
7
6
DTCE6
DTCE5
0
0
R/W
R/W
DTC Activation Enable
0
1
6
5
IRQ1
IRQ2
IRQ9
IRQ10
ADI
TGI0A
TGI2B
TGI3A
TGI5B
DMTEND0B
DMTEND1A
TXI2
RXI3
H'FF28 to H'FF2F
5
4
DTCE4
DTCE3
0
0
R/W
R/W
DTC activation by interrupt is disabled
[Clearing conditions]
• When data transfer ends with the DISEL bit set to 1
• When the specified number of transfers end
DTC activation by this interrupt is enabled
[Hold condition]
When the DISEL bit is 0 and the specified number of
transfers have not ended
Bits
4
3
IRQ3
IRQ4
IRQ11
IRQ12
TGI0B
TGI0C
TGI3B
TGI3C
CMIA0
DMTEND1B
RXI0
TXI3
RXI4
3
2
DTCE2
DTCE1
0
0
R/W
R/W
2
1
IRQ5
IRQ6
IRQ13
IRQ14
TGI0D
TGI1A
TGI3D
TGI4A
CMIB0
CMIA1
TXI0
RXI1
TXI4
DTC
1
0
DTCE0
0
0
R/W
0
IRQ7
IRQ15
TGI1B
TGI4B
CMIB1
TXI1

Advertisement

Table of Contents
loading

Table of Contents