Hitachi H8S/2678 Series Reference Manual page 445

Timing of On-Chip Supporting Modules
Table 7.18 Timing of On-Chip Supporting Modules
Condition A*: V
CC
V
SS
specifications), T
Condition B: V
CC
V
SS
specifications), T
* In planning stage
Item
I/O ports Output data delay
time
Input data setup time t
Input data hold time
PPG Pulse output delay
time
TPU Timer output delay
time
Timer input setup
time
Timer clock input
setup time
Timer Single-edge
clock specification
pulse
Both-edge
width
specification
8-bit Timer output delay
timer time
Timer reset input
setup time
Timer clock input
setup time
Timer Single-edge
clock specification
pulse
Both-edge
width
specification
428
= 2.7 V to 3.6 V, AV
= AV = 0 V, ø = 2 MHz to 20 MHz, T
SS
= –40°C to +85°C (wide-range specifications)
a
= 3.0 V to 3.6 V, AV
= AV = 0 V, ø = 2 MHz to 33 MHz, T
SS
= –40°C to +85°C (wide-range specifications)
a
Symbol
t
PWD
PRS
t
PRH
t
POD
t
TOCD
t
TICS
t
TCKS
t
TCKWH
t
TCKWL
t
TMOD
t
TMRS
t
TMCS
t
TMCWH
t
TMCWL
= 2.7 V to 3.6 V, V
CC
a
= 3.0 V to 3.6 V, V
CC
a
Condition A
Min Max
— 50
30 —
30 —
— 50
— 50
30 —
30 —
1.5 —
2.5 —
— 50
30 —
30 —
1.5 —
2.5 —
= 2.7 V to AV
ref CC
= –20°C to +75°C (regular
= 3.0 V to AV
ref CC
= –20°C to +75°C (regular
Condition B
Min Max Unit
— 40 ns
25 — ns
25 — ns
— 40 ns
— 40 ns
25 — ns
25 — ns
1.5 — t
cyc
2.5 — t
cyc
— 40 ns
25 — ns
25 — ns
1.5 — t
cyc
2.5 — t
cyc
,
,
Test
Conditions
Figure 7.29
Figure 7.30
Figure 7.31
Figure 7.32
Figure 7.33
Figure 7.35
Figure 7.34