Hitachi H8S/2678 Series Reference Manual page 302

Bits 7 to 0—CS7 to CS0 Enable (CS7E to CS0E): These bits enable or disable the
corresponding CSn output.
Bit n
CSnE Description
Pin is designated as I/O port and does not function as CSn output pin
0
Pin is designated as CSn output pin
1
5.16.3 Pin Functions
Port G pins also function as bus control signal output pins (BREQ, BACK, BREQO, and CS3 to
CS0). Port G pin functions are shown in table 5.35.
Table 5.35 Port G Pin Functions
Pin Selection Method and Pin Functions
PG6/BREQ The pin function is switched as shown below according to the operating mode, bit
EXPE, bit BRLE, and bit PG6DDR.
Operating
mode
EXPE
BRLE
PG6DDR
Pin function
PG5/BACK The pin function is switched as shown below according to the operating mode, bit
EXPE, bit BRLE, and bit PG5DDR.
Operating
mode
EXPE
BRLE
PG5DDR
Pin function
1, 2, 4, 5, 6
—
0 1
0 1 —
BREQ
PG6 PG6
input output input
pin pin pin
1, 2, 4, 5, 6
—
0 1
0 1 —
BACK
PG5 PG5
input output output
pin pin pin
7
0
—
0 1 0
PG6 PG6 PG6
input output input
pin pin pin
7
0
—
0 1 0
PG5 PG5 PG5
input output input
pin pin pin
(Initial value)
(n = 7 to 0)
1
0 1
1 —
BREQ
PG6
output input
pin pin
1
0 1
1 —
BACK
PG5
output output
pin pin
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