Table of Contents
Advertisement
5.15.2
Register Configuration
Table 5.32 shows the port F register configuration.
Table 5.32 Port F Registers
Name
Port F data direction register
Port F data register
Port F register
Port function control register 2
Notes: 1. Lower 16 bits of the address.
2. Initial value depends on the mode.
Port F Data Direction Register (PFDDR)
Bit
7
PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR
Modes 1, 2, 4, 5, 6
Initial value
1
Read/Write
W
Mode 7
Initial value
0
Read/Write
W
PFDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port F. PFDDR cannot be read; if it is, an undefined value will be read.
PFDDR is initialized by a reset and in hardware standby mode, to H'80 in modes 1, 2, 4, 5, and 6,
and to H'00 in mode 7. It retains its prior state in software standby mode. The OPE bit in SBYCR
is used to select whether the bus control output pins retain their output state or become high-
impedance when a transition is made to software standby mode.
• Modes 1, 2, 4, 5, and 6
Pin PF7 functions as the ø output pin when the corresponding PFDDR bit is set to 1, and as an
input port when the bit is cleared to 0.
Pin PF6 functions as the AS output pin when ASOE is set to 1. When ASOE is cleared to 0,
pin PF6 is an I/O port and its function can be switched with PF6DDR.
The input/output direction specification in PFDDR is ignored for pins PF5 and PF4, which are
automatically designated as bus control outputs ( RD and HWR).
Abbreviation
PFDDR
PFDR
PORTF
PFCR2
6
5
0
0
W
W
0
0
W
W
R/W
Initial Value
W
H'80/H'00*
R/W
H'00
R
Undefined
R/W
H'0E
4
3
0
0
W
W
0
0
W
W
Address*
2
H'FE2E
H'FF6E
H'FF5E
H'FE34
2
1
0
0
W
W
0
0
W
W
1
0
0
W
0
W
275
Advertisement
Table of Contents
