Hitachi H8S/2678 Series Reference Manual page 552

ETCR1A—Transfer Count Register 1A
Bit
ETCR1A
Initial value
Read/Write
Sequential mode
Idle mode
Normal mode
Repeat mode
Block transfer mode
*: Undefined
MAR1BH—Memory Address Register 1BH
MAR1BL—Memory Address Register 1BL
31
Bit
MAR1BH —
Initial value 0
—
Read/Write
Bit 15
MAR1BL
Initial value *
R/W
Read/Write
In short address mode: Specifies transfer destination/transfer source address
In full address mode:
*: Undefined
15 14 13 12
* * * *
R/W R/W R/W R/W
Holds number of transfers
Holds block size
30 29 28 27
— — — —
0 0 0 0
— — — —
14 13 12 11
* * * *
R/W R/W R/W R/W
H'FEF6
11 10 9 8
* * * *
R/W R/W R/W R/W R/W
Transfer counter
H'FEF8
H'FEFA
26 25 24 23
— — —
0 0 0 *
— — — R/W
10 9 8 7
* * * *
R/W R/W R/W R/W
Not used
7 6 5 4 3
* * * * *
R/W R/W R/W R/W
Transfer counter
Block size counter
22 21 20 19
* * * *
R/W R/W R/W R/W
6 5 4 3
* * * *
R/W R/W R/W R/W
DMAC
2 1 0
* * *
R/W R/W R/W
DMAC
DMAC
18 17 16
* * *
R/W R/W R/W
2 1 0
* * *
R/W R/W R/W
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