Hitachi H8S/2678 Series Reference Manual page 148

16-Bit, 3-State Access Space: Figures 4.14 to 4.16 show bus timings for a 16-bit, 3-state access
space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used
for the odd address, and the lower half (D7 to D0) for the even address.
Wait states can be inserted.
ø
Address bus
CSn
AS
RD
D15 to D8
Read
D7 to D0
HWR
LWR
Write
D15 to D8
D7 to D0
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 4.14 Bus Timing for 16-Bit, 3-State Access Space (1)
Bus cycle
T
1
High
High impedance
(Even Address Byte Access)
T T
2 3
Valid
Valid
Invalid
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