Hitachi H8S/2678 Series Reference Manual page 549

ETCR0A—Transfer Count Register 0A
Bit
ETCR0A
Initial value
Read/Write
Sequential mode
and idle mode
Normal mode
Repeat mode
Block transfer mode
*: Undefined
MAR0BH—Memory Address Register 0BH
MAR0BL—Memory Address Register 0BL
31
Bit
MAR0BH —
Initial value 0
—
Read/Write
Bit 15
MAR0BL
Initial value *
R/W
Read/Write
In short address mode: Specifies transfer destination/transfer source address
In full address mode:
*: Undefined
532
15 14 13 12
* * * *
R/W R/W R/W R/W
Holds number of transfers
Holds block size
30 29 28 27
— — — —
0 0 0 0
— — — —
14 13 12 11
* * * *
R/W R/W R/W R/W
H'FEE6
11 10 9 8
* * * *
R/W R/W R/W R/W R/W
Transfer counter
H'FEE8
H'FEEA
26 25 24 23
— — —
0 0 0 *
— — — R/W
10 9 8 7
* * * *
R/W R/W R/W R/W
Specifies transfer destination
7 6 5 4 3
* * * * *
R/W R/W R/W R/W
Transfer counter
Block size counter
22 21 20 19
* * * *
R/W R/W R/W R/W
6 5 4 3
* * * *
R/W R/W R/W R/W
DMAC
2 1 0
* * *
R/W R/W R/W
DMAC
DMAC
18 17 16
* * *
R/W R/W R/W
2 1 0
* * *
R/W R/W R/W